Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores

Yinhe HAN; Yu HU; Xiaowei LI; Huawei LI; Anshuman CHANDRA; Xiaoqing WEN

doi:10.1093/ietisy/e88-d.9.2126

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores

Yinhe HAN, Yu HU, Xiaowei LI, Huawei LI, Anshuman CHANDRA, Xiaoqing WEN

Full Text Views

0

Share
Cite this

Summary :

Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match of TAM and internal scan chains. However, conventional serial connection of internal scan chains incurs power and time penalty. Study shows that the distribution and high density of don't care bits (X-bits) in test patterns make scan slices overlapping and partial overlapping possible. A novel parallel CWD (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern: partition and fill, is presented. Experimental results on d695 of ITC2002 benchmark demonstrated the shift time and test power have been decreased by 1.5 and 15 times, respectively. In addition, the proposed pCWD can be used as a stand-alone time reduction technique, which has better performance than previous techniques.

Publication: IEICE TRANSACTIONS on Information Vol.E88-D No.9 pp.2126-2134

Publication Date: 2005/09/01

Publicized

Online ISSN

DOI: 10.1093/ietisy/e88-d.9.2126

Type of Manuscript: PAPER

Category: Dependable Computing

Cite this

Copy

Yinhe HAN, Yu HU, Xiaowei LI, Huawei LI, Anshuman CHANDRA, Xiaoqing WEN, "Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores" in IEICE TRANSACTIONS on Information, vol. E88-D, no. 9, pp. 2126-2134, September 2005, doi: 10.1093/ietisy/e88-d.9.2126.
Abstract: Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match of TAM and internal scan chains. However, conventional serial connection of internal scan chains incurs power and time penalty. Study shows that the distribution and high density of don't care bits (X-bits) in test patterns make scan slices overlapping and partial overlapping possible. A novel parallel CWD (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern: partition and fill, is presented. Experimental results on d695 of ITC2002 benchmark demonstrated the shift time and test power have been decreased by 1.5 and 15 times, respectively. In addition, the proposed pCWD can be used as a stand-alone time reduction technique, which has better performance than previous techniques.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.9.2126/_p

Copy

@ARTICLE{e88-d_9_2126,
author={Yinhe HAN, Yu HU, Xiaowei LI, Huawei LI, Anshuman CHANDRA, Xiaoqing WEN, },
journal={IEICE TRANSACTIONS on Information},
title={Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores},
year={2005},
volume={E88-D},
number={9},
pages={2126-2134},
abstract={Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match of TAM and internal scan chains. However, conventional serial connection of internal scan chains incurs power and time penalty. Study shows that the distribution and high density of don't care bits (X-bits) in test patterns make scan slices overlapping and partial overlapping possible. A novel parallel CWD (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern: partition and fill, is presented. Experimental results on d695 of ITC2002 benchmark demonstrated the shift time and test power have been decreased by 1.5 and 15 times, respectively. In addition, the proposed pCWD can be used as a stand-alone time reduction technique, which has better performance than previous techniques.},
keywords={},
doi={10.1093/ietisy/e88-d.9.2126},
ISSN={},
month={September},}

Copy

TY - JOUR
TI - Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores
T2 - IEICE TRANSACTIONS on Information
SP - 2126
EP - 2134
AU - Yinhe HAN
AU - Yu HU
AU - Xiaowei LI
AU - Huawei LI
AU - Anshuman CHANDRA
AU - Xiaoqing WEN
PY - 2005
DO - 10.1093/ietisy/e88-d.9.2126
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2005
AB - Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match of TAM and internal scan chains. However, conventional serial connection of internal scan chains incurs power and time penalty. Study shows that the distribution and high density of don't care bits (X-bits) in test patterns make scan slices overlapping and partial overlapping possible. A novel parallel CWD (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern: partition and fill, is presented. Experimental results on d695 of ITC2002 benchmark demonstrated the shift time and test power have been decreased by 1.5 and 15 times, respectively. In addition, the proposed pCWD can be used as a stand-alone time reduction technique, which has better performance than previous techniques.
ER -