Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time

Yu HU; Yinhe HAN; Xiaowei LI; Huawei LI; Xiaoqing WEN

doi:10.1093/ietisy/e89-d.10.2616

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time

Yu HU, Yinhe HAN, Xiaowei LI, Huawei LI, Xiaoqing WEN

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LSI testing is critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-testability technique for LSI design and testing, there is a strong need to reduce the test data Volume, scan-in Power dissipation, and test application Time (VPT) of full-scan testing. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme to tackle all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3%, and 85.5% reduction effects in test data volume, average scan-in power dissipation, peak scan-in power dissipation, and test application time, respectively.

Publication: IEICE TRANSACTIONS on Information Vol.E89-D No.10 pp.2616-2625

Publication Date: 2006/10/01

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Online ISSN: 1745-1361

DOI: 10.1093/ietisy/e89-d.10.2616

Type of Manuscript: PAPER

Category: Dependable Computing

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Yu HU, Yinhe HAN, Xiaowei LI, Huawei LI, Xiaoqing WEN, "Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time" in IEICE TRANSACTIONS on Information, vol. E89-D, no. 10, pp. 2616-2625, October 2006, doi: 10.1093/ietisy/e89-d.10.2616.
Abstract: LSI testing is critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-testability technique for LSI design and testing, there is a strong need to reduce the test data Volume, scan-in Power dissipation, and test application Time (VPT) of full-scan testing. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme to tackle all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3%, and 85.5% reduction effects in test data volume, average scan-in power dissipation, peak scan-in power dissipation, and test application time, respectively.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e89-d.10.2616/_p

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@ARTICLE{e89-d_10_2616,
author={Yu HU, Yinhe HAN, Xiaowei LI, Huawei LI, Xiaoqing WEN, },
journal={IEICE TRANSACTIONS on Information},
title={Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time},
year={2006},
volume={E89-D},
number={10},
pages={2616-2625},
abstract={LSI testing is critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-testability technique for LSI design and testing, there is a strong need to reduce the test data Volume, scan-in Power dissipation, and test application Time (VPT) of full-scan testing. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme to tackle all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3%, and 85.5% reduction effects in test data volume, average scan-in power dissipation, peak scan-in power dissipation, and test application time, respectively.},
keywords={},
doi={10.1093/ietisy/e89-d.10.2616},
ISSN={1745-1361},
month={October},}

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TY - JOUR
TI - Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time
T2 - IEICE TRANSACTIONS on Information
SP - 2616
EP - 2625
AU - Yu HU
AU - Yinhe HAN
AU - Xiaowei LI
AU - Huawei LI
AU - Xiaoqing WEN
PY - 2006
DO - 10.1093/ietisy/e89-d.10.2616
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E89-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2006
AB - LSI testing is critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-testability technique for LSI design and testing, there is a strong need to reduce the test data Volume, scan-in Power dissipation, and test application Time (VPT) of full-scan testing. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme to tackle all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3%, and 85.5% reduction effects in test data volume, average scan-in power dissipation, peak scan-in power dissipation, and test application time, respectively.
ER -