A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder

Wei-min WANG; Du-yan BI; Xing-min DU; Lin-hua MA

doi:10.1093/ietisy/e90-d.8.1301

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Wei-min WANG, Du-yan BI, Xing-min DU, Lin-hua MA, "A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder" in IEICE TRANSACTIONS on Information, vol. E90-D, no. 8, pp. 1301-1303, August 2007, doi: 10.1093/ietisy/e90-d.8.1301.
Abstract: A novel high-speed and area-efficient Reed-Solomon decoder is proposed, which employs pipelining architecture of minimized modified Euclid (ME) algorithm. The logic synthesis and simulation results of its VLSI implementation show that it not only can operate at a higher clock frequency, but also consumes fewer hardware resources.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e90-d.8.1301/_p

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@ARTICLE{e90-d_8_1301,
author={Wei-min WANG, Du-yan BI, Xing-min DU, Lin-hua MA, },
journal={IEICE TRANSACTIONS on Information},
title={A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder},
year={2007},
volume={E90-D},
number={8},
pages={1301-1303},
abstract={A novel high-speed and area-efficient Reed-Solomon decoder is proposed, which employs pipelining architecture of minimized modified Euclid (ME) algorithm. The logic synthesis and simulation results of its VLSI implementation show that it not only can operate at a higher clock frequency, but also consumes fewer hardware resources.},
keywords={},
doi={10.1093/ietisy/e90-d.8.1301},
ISSN={1745-1361},
month={August},}

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TY - JOUR
TI - A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder
T2 - IEICE TRANSACTIONS on Information
SP - 1301
EP - 1303
AU - Wei-min WANG
AU - Du-yan BI
AU - Xing-min DU
AU - Lin-hua MA
PY - 2007
DO - 10.1093/ietisy/e90-d.8.1301
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2007
AB - A novel high-speed and area-efficient Reed-Solomon decoder is proposed, which employs pipelining architecture of minimized modified Euclid (ME) algorithm. The logic synthesis and simulation results of its VLSI implementation show that it not only can operate at a higher clock frequency, but also consumes fewer hardware resources.
ER -