Area-Time Efficient Modulo 2<SUP><I>n</I></SUP>-1 Adder Design Using Hybrid Carry Selection

Su-Hon LIN; Ming-Hwa SHEU

doi:10.1093/ietisy/e91-d.2.361

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Su-Hon LIN, Ming-Hwa SHEU, "Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection" in IEICE TRANSACTIONS on Information, vol. E91-D, no. 2, pp. 361-362, February 2008, doi: 10.1093/ietisy/e91-d.2.361.
Abstract: A new Hybrid-Carry-Selection (HCS) approach for deriving an efficient modulo 2ⁿ-1 addition is presented in this study. Its resulting adder architecture is simple and applicable for all n values. Based on 180-nm CMOS technology, the HCS-based modulo 2ⁿ-1 adder demonstrates its superiority in Area-Time (AT) performance over existing solutions.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.2.361/_p

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@ARTICLE{e91-d_2_361,
author={Su-Hon LIN, Ming-Hwa SHEU, },
journal={IEICE TRANSACTIONS on Information},
title={Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection},
year={2008},
volume={E91-D},
number={2},
pages={361-362},
abstract={A new Hybrid-Carry-Selection (HCS) approach for deriving an efficient modulo 2ⁿ-1 addition is presented in this study. Its resulting adder architecture is simple and applicable for all n values. Based on 180-nm CMOS technology, the HCS-based modulo 2ⁿ-1 adder demonstrates its superiority in Area-Time (AT) performance over existing solutions.},
keywords={},
doi={10.1093/ietisy/e91-d.2.361},
ISSN={1745-1361},
month={February},}

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TY - JOUR
TI - Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection
T2 - IEICE TRANSACTIONS on Information
SP - 361
EP - 362
AU - Su-Hon LIN
AU - Ming-Hwa SHEU
PY - 2008
DO - 10.1093/ietisy/e91-d.2.361
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2008
AB - A new Hybrid-Carry-Selection (HCS) approach for deriving an efficient modulo 2ⁿ-1 addition is presented in this study. Its resulting adder architecture is simple and applicable for all n values. Based on 180-nm CMOS technology, the HCS-based modulo 2ⁿ-1 adder demonstrates its superiority in Area-Time (AT) performance over existing solutions.
ER -