Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors

Masato NAKAZATO; Michiko INOUE; Satoshi OHTAKE; Hideo FUJIWARA

doi:10.1093/ietisy/e91-d.3.763

Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors

Masato NAKAZATO, Michiko INOUE, Satoshi OHTAKE, Hideo FUJIWARA

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In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.

Publication: IEICE TRANSACTIONS on Information Vol.E91-D No.3 pp.763-770

Publication Date: 2008/03/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1093/ietisy/e91-d.3.763

Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs)

Category: High-Level Testing

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Masato NAKAZATO, Michiko INOUE, Satoshi OHTAKE, Hideo FUJIWARA, "Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors" in IEICE TRANSACTIONS on Information, vol. E91-D, no. 3, pp. 763-770, March 2008, doi: 10.1093/ietisy/e91-d.3.763.
Abstract: In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.3.763/_p

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@ARTICLE{e91-d_3_763,
author={Masato NAKAZATO, Michiko INOUE, Satoshi OHTAKE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors},
year={2008},
volume={E91-D},
number={3},
pages={763-770},
abstract={In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.},
keywords={},
doi={10.1093/ietisy/e91-d.3.763},
ISSN={1745-1361},
month={March},}

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TY - JOUR
TI - Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
T2 - IEICE TRANSACTIONS on Information
SP - 763
EP - 770
AU - Masato NAKAZATO
AU - Michiko INOUE
AU - Satoshi OHTAKE
AU - Hideo FUJIWARA
PY - 2008
DO - 10.1093/ietisy/e91-d.3.763
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2008
AB - In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.
ER -