Integrated Design and Test Assistance for Pipeline Controllers

Hiroaki IWASHITA; Tsuneo NAKATA; Fumiyasu HIROSE

Integrated Design and Test Assistance for Pipeline Controllers

Hiroaki IWASHITA, Tsuneo NAKATA, Fumiyasu HIROSE

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We Propose an integrated design and test assistance method for pipelined processors. Our approach generates behavioral-level test environments for pipeline control mechanisms from a machine-readable specification. It includes automatic generation of test programs and behavioral descriptions. Verification can be done by applying logic simulation to both the designers' descriptions and the behavioral descriptions, and then comparing the results. We have implemented an experimental system that enumerates all hazard patterns--instruction patterns that cause pipeline hazards--from the specifications, and generates the test programs and the behavioral descriptions for the pipeline controllers. The test programs cover all of the hazard patterns. The behavioral descriptions can manipulate any instruction stream. Experimental results for several RISC processors show that actual hazard patterns are too numerous to be easily enumerated by hand. Using workstations, our system can generate the test programs that cover all of the patterns, taking a few minutes. Results suggest that the system can be used to evaluate pipeline design.

Publication: IEICE TRANSACTIONS on Information Vol.E76-D No.7 pp.747-754

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design)

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Hiroaki IWASHITA, Tsuneo NAKATA, Fumiyasu HIROSE, "Integrated Design and Test Assistance for Pipeline Controllers" in IEICE TRANSACTIONS on Information, vol. E76-D, no. 7, pp. 747-754, July 1993, doi: .
Abstract: We Propose an integrated design and test assistance method for pipelined processors. Our approach generates behavioral-level test environments for pipeline control mechanisms from a machine-readable specification. It includes automatic generation of test programs and behavioral descriptions. Verification can be done by applying logic simulation to both the designers' descriptions and the behavioral descriptions, and then comparing the results. We have implemented an experimental system that enumerates all hazard patterns--instruction patterns that cause pipeline hazards--from the specifications, and generates the test programs and the behavioral descriptions for the pipeline controllers. The test programs cover all of the hazard patterns. The behavioral descriptions can manipulate any instruction stream. Experimental results for several RISC processors show that actual hazard patterns are too numerous to be easily enumerated by hand. Using workstations, our system can generate the test programs that cover all of the patterns, taking a few minutes. Results suggest that the system can be used to evaluate pipeline design.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e76-d_7_747/_p

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@ARTICLE{e76-d_7_747,
author={Hiroaki IWASHITA, Tsuneo NAKATA, Fumiyasu HIROSE, },
journal={IEICE TRANSACTIONS on Information},
title={Integrated Design and Test Assistance for Pipeline Controllers},
year={1993},
volume={E76-D},
number={7},
pages={747-754},
abstract={We Propose an integrated design and test assistance method for pipelined processors. Our approach generates behavioral-level test environments for pipeline control mechanisms from a machine-readable specification. It includes automatic generation of test programs and behavioral descriptions. Verification can be done by applying logic simulation to both the designers' descriptions and the behavioral descriptions, and then comparing the results. We have implemented an experimental system that enumerates all hazard patterns--instruction patterns that cause pipeline hazards--from the specifications, and generates the test programs and the behavioral descriptions for the pipeline controllers. The test programs cover all of the hazard patterns. The behavioral descriptions can manipulate any instruction stream. Experimental results for several RISC processors show that actual hazard patterns are too numerous to be easily enumerated by hand. Using workstations, our system can generate the test programs that cover all of the patterns, taking a few minutes. Results suggest that the system can be used to evaluate pipeline design.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Integrated Design and Test Assistance for Pipeline Controllers
T2 - IEICE TRANSACTIONS on Information
SP - 747
EP - 754
AU - Hiroaki IWASHITA
AU - Tsuneo NAKATA
AU - Fumiyasu HIROSE
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1993
AB - We Propose an integrated design and test assistance method for pipelined processors. Our approach generates behavioral-level test environments for pipeline control mechanisms from a machine-readable specification. It includes automatic generation of test programs and behavioral descriptions. Verification can be done by applying logic simulation to both the designers' descriptions and the behavioral descriptions, and then comparing the results. We have implemented an experimental system that enumerates all hazard patterns--instruction patterns that cause pipeline hazards--from the specifications, and generates the test programs and the behavioral descriptions for the pipeline controllers. The test programs cover all of the hazard patterns. The behavioral descriptions can manipulate any instruction stream. Experimental results for several RISC processors show that actual hazard patterns are too numerous to be easily enumerated by hand. Using workstations, our system can generate the test programs that cover all of the patterns, taking a few minutes. Results suggest that the system can be used to evaluate pipeline design.
ER -