The Effect of CMOS VLSI IDDq Measurement on Defect Level

Junichi HIRASE; Masanori HAMADA

The Effect of CMOS VLSI IDDq Measurement on Defect Level

Junichi HIRASE, Masanori HAMADA

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In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.

Publication: IEICE TRANSACTIONS on Information Vol.E78-D No.7 pp.839-844

Publication Date: 1995/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)

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Junichi HIRASE, Masanori HAMADA, "The Effect of CMOS VLSI IDDq Measurement on Defect Level" in IEICE TRANSACTIONS on Information, vol. E78-D, no. 7, pp. 839-844, July 1995, doi: .
Abstract: In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e78-d_7_839/_p

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@ARTICLE{e78-d_7_839,
author={Junichi HIRASE, Masanori HAMADA, },
journal={IEICE TRANSACTIONS on Information},
title={The Effect of CMOS VLSI IDDq Measurement on Defect Level},
year={1995},
volume={E78-D},
number={7},
pages={839-844},
abstract={In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - The Effect of CMOS VLSI IDDq Measurement on Defect Level
T2 - IEICE TRANSACTIONS on Information
SP - 839
EP - 844
AU - Junichi HIRASE
AU - Masanori HAMADA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E78-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1995
AB - In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.
ER -