Estimating Interconnection Lengths in Three-Dimensional Computer Systems

Dirk STROOBANDT; Jan VAN CAMPENHOUT

Estimating Interconnection Lengths in Three-Dimensional Computer Systems

Dirk STROOBANDT, Jan VAN CAMPENHOUT

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In computer hardware there is a constant evolution towards smaller transistor sizes. At the same time, more and more transistors are placed on one chip. Both trends make the pin limitation problem worse. Scaling down chip sizes adds to the shortage of available pins while increasing the number of transistors per chip imposes a higher need for chip terminals. The use of three-dimensional systems would alleviate this pin limitation problem. In order to decide whether the benefits of such systems balance the higher processing costs, one must be able to characterize these benefits accurately. This can be done by estimating important layout properties of electronic designs, such as space requirements and interconnection length values. For a two-dimensional placement, Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2 which is not sufficiently accurate for some applications. In this paper, we first extend Donath's technique to a three-dimensional placement. We then compute a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.

Publication: IEICE TRANSACTIONS on Information Vol.E80-D No.10 pp.1024-1031

Publication Date: 1997/10/25

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Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)

Category: Physical Design

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Dirk STROOBANDT, Jan VAN CAMPENHOUT, "Estimating Interconnection Lengths in Three-Dimensional Computer Systems" in IEICE TRANSACTIONS on Information, vol. E80-D, no. 10, pp. 1024-1031, October 1997, doi: .
Abstract: In computer hardware there is a constant evolution towards smaller transistor sizes. At the same time, more and more transistors are placed on one chip. Both trends make the pin limitation problem worse. Scaling down chip sizes adds to the shortage of available pins while increasing the number of transistors per chip imposes a higher need for chip terminals. The use of three-dimensional systems would alleviate this pin limitation problem. In order to decide whether the benefits of such systems balance the higher processing costs, one must be able to characterize these benefits accurately. This can be done by estimating important layout properties of electronic designs, such as space requirements and interconnection length values. For a two-dimensional placement, Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2 which is not sufficiently accurate for some applications. In this paper, we first extend Donath's technique to a three-dimensional placement. We then compute a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e80-d_10_1024/_p

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@ARTICLE{e80-d_10_1024,
author={Dirk STROOBANDT, Jan VAN CAMPENHOUT, },
journal={IEICE TRANSACTIONS on Information},
title={Estimating Interconnection Lengths in Three-Dimensional Computer Systems},
year={1997},
volume={E80-D},
number={10},
pages={1024-1031},
abstract={In computer hardware there is a constant evolution towards smaller transistor sizes. At the same time, more and more transistors are placed on one chip. Both trends make the pin limitation problem worse. Scaling down chip sizes adds to the shortage of available pins while increasing the number of transistors per chip imposes a higher need for chip terminals. The use of three-dimensional systems would alleviate this pin limitation problem. In order to decide whether the benefits of such systems balance the higher processing costs, one must be able to characterize these benefits accurately. This can be done by estimating important layout properties of electronic designs, such as space requirements and interconnection length values. For a two-dimensional placement, Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2 which is not sufficiently accurate for some applications. In this paper, we first extend Donath's technique to a three-dimensional placement. We then compute a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Estimating Interconnection Lengths in Three-Dimensional Computer Systems
T2 - IEICE TRANSACTIONS on Information
SP - 1024
EP - 1031
AU - Dirk STROOBANDT
AU - Jan VAN CAMPENHOUT
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1997
AB - In computer hardware there is a constant evolution towards smaller transistor sizes. At the same time, more and more transistors are placed on one chip. Both trends make the pin limitation problem worse. Scaling down chip sizes adds to the shortage of available pins while increasing the number of transistors per chip imposes a higher need for chip terminals. The use of three-dimensional systems would alleviate this pin limitation problem. In order to decide whether the benefits of such systems balance the higher processing costs, one must be able to characterize these benefits accurately. This can be done by estimating important layout properties of electronic designs, such as space requirements and interconnection length values. For a two-dimensional placement, Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2 which is not sufficiently accurate for some applications. In this paper, we first extend Donath's technique to a three-dimensional placement. We then compute a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.
ER -