High-Fair Bus Arbiter for Multiprocessors

Chiung-San LEE

High-Fair Bus Arbiter for Multiprocessors

Chiung-San LEE

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This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.

Publication: IEICE TRANSACTIONS on Information Vol.E80-D No.1 pp.94-97

Publication Date: 1997/01/25

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Category: Algorithm and Computational Complexity

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Chiung-San LEE, "High-Fair Bus Arbiter for Multiprocessors" in IEICE TRANSACTIONS on Information, vol. E80-D, no. 1, pp. 94-97, January 1997, doi: .
Abstract: This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e80-d_1_94/_p

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@ARTICLE{e80-d_1_94,
author={Chiung-San LEE, },
journal={IEICE TRANSACTIONS on Information},
title={High-Fair Bus Arbiter for Multiprocessors},
year={1997},
volume={E80-D},
number={1},
pages={94-97},
abstract={This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.},
keywords={},
doi={},
ISSN={},
month={January},}

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TY - JOUR
TI - High-Fair Bus Arbiter for Multiprocessors
T2 - IEICE TRANSACTIONS on Information
SP - 94
EP - 97
AU - Chiung-San LEE
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 1997
AB - This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.
ER -