Address Addition and Decoding without Carry Propagation

Yung-Hei LEE; Seung Ho HWANG

Address Addition and Decoding without Carry Propagation

Yung-Hei LEE, Seung Ho HWANG

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The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.

Publication: IEICE TRANSACTIONS on Information Vol.E80-D No.1 pp.98-100

Publication Date: 1997/01/25

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Category: Algorithm and Computational Complexity

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Yung-Hei LEE, Seung Ho HWANG, "Address Addition and Decoding without Carry Propagation" in IEICE TRANSACTIONS on Information, vol. E80-D, no. 1, pp. 98-100, January 1997, doi: .
Abstract: The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e80-d_1_98/_p

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@ARTICLE{e80-d_1_98,
author={Yung-Hei LEE, Seung Ho HWANG, },
journal={IEICE TRANSACTIONS on Information},
title={Address Addition and Decoding without Carry Propagation},
year={1997},
volume={E80-D},
number={1},
pages={98-100},
abstract={The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.},
keywords={},
doi={},
ISSN={},
month={January},}

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TY - JOUR
TI - Address Addition and Decoding without Carry Propagation
T2 - IEICE TRANSACTIONS on Information
SP - 98
EP - 100
AU - Yung-Hei LEE
AU - Seung Ho HWANG
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 1997
AB - The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.
ER -