Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations

Yang SONG; Zhenyu LIU; Takeshi IKENAGA; Satoshi GOTO

Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations

Yang SONG, Zhenyu LIU, Takeshi IKENAGA, Satoshi GOTO

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This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7% computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3% power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8% power consumption with 1.73 K gates overhead.

Publication: IEICE TRANSACTIONS on Information Vol.E90-D No.1 pp.108-117

Publication Date: 2007/01/01

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Online ISSN: 1745-1361

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Type of Manuscript: Special Section PAPER (Special Section on Advanced Image Technology)

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Yang SONG, Zhenyu LIU, Takeshi IKENAGA, Satoshi GOTO, "Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations" in IEICE TRANSACTIONS on Information, vol. E90-D, no. 1, pp. 108-117, January 2007, doi: .
Abstract: This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7% computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3% power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8% power consumption with 1.73 K gates overhead.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e90-d_1_108/_p

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@ARTICLE{e90-d_1_108,
author={Yang SONG, Zhenyu LIU, Takeshi IKENAGA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Information},
title={Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations},
year={2007},
volume={E90-D},
number={1},
pages={108-117},
abstract={This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7% computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3% power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8% power consumption with 1.73 K gates overhead.},
keywords={},
doi={},
ISSN={1745-1361},
month={January},}

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TY - JOUR
TI - Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations
T2 - IEICE TRANSACTIONS on Information
SP - 108
EP - 117
AU - Yang SONG
AU - Zhenyu LIU
AU - Takeshi IKENAGA
AU - Satoshi GOTO
PY - 2007
DO -
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2007
AB - This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7% computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3% power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8% power consumption with 1.73 K gates overhead.
ER -