Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability

Masato NAKAZATO; Satoshi OHTAKE; Kewal K. SALUJA; Hideo FUJIWARA

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability

Masato NAKAZATO, Satoshi OHTAKE, Kewal K. SALUJA, Hideo FUJIWARA

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In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.

Publication: IEICE TRANSACTIONS on Information Vol.E90-D No.1 pp.296-305

Publication Date: 2007/01/01

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Online ISSN: 1745-1361

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Type of Manuscript: PAPER

Category: Dependable Computing

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Masato NAKAZATO, Satoshi OHTAKE, Kewal K. SALUJA, Hideo FUJIWARA, "Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability" in IEICE TRANSACTIONS on Information, vol. E90-D, no. 1, pp. 296-305, January 2007, doi: .
Abstract: In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e90-d_1_296/_p

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@ARTICLE{e90-d_1_296,
author={Masato NAKAZATO, Satoshi OHTAKE, Kewal K. SALUJA, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability},
year={2007},
volume={E90-D},
number={1},
pages={296-305},
abstract={In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.},
keywords={},
doi={},
ISSN={1745-1361},
month={January},}

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TY - JOUR
TI - Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability
T2 - IEICE TRANSACTIONS on Information
SP - 296
EP - 305
AU - Masato NAKAZATO
AU - Satoshi OHTAKE
AU - Kewal K. SALUJA
AU - Hideo FUJIWARA
PY - 2007
DO -
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2007
AB - In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.
ER -