LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

Yu HU; Jing YE; Zhiping SHI; Xiaowei LI

doi:10.1587/transinf.2016EDP7184

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

Yu HU, Jing YE, Zhiping SHI, Xiaowei LI

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Summary :

Process variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.

Publication: IEICE TRANSACTIONS on Information Vol.E100-D No.2 pp.323-331

Publication Date: 2017/02/01

Publicized: 2016/10/25

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2016EDP7184

Type of Manuscript: PAPER

Category: Dependable Computing

Authors

Yu HU
  Capital Normal University,Chinese Academy of Sciences
Jing YE
  Chinese Academy of Sciences
Zhiping SHI
  Capital Normal University
Xiaowei LI
  Chinese Academy of Sciences

Keyword

process variation, timing variation, sample, path selection, least square

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Yu HU, Jing YE, Zhiping SHI, Xiaowei LI, "LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization" in IEICE TRANSACTIONS on Information, vol. E100-D, no. 2, pp. 323-331, February 2017, doi: 10.1587/transinf.2016EDP7184.
Abstract: Process variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.2016EDP7184/_p

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@ARTICLE{e100-d_2_323,
author={Yu HU, Jing YE, Zhiping SHI, Xiaowei LI, },
journal={IEICE TRANSACTIONS on Information},
title={LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization},
year={2017},
volume={E100-D},
number={2},
pages={323-331},
abstract={Process variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.},
keywords={},
doi={10.1587/transinf.2016EDP7184},
ISSN={1745-1361},
month={February},}

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TY - JOUR
TI - LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization
T2 - IEICE TRANSACTIONS on Information
SP - 323
EP - 331
AU - Yu HU
AU - Jing YE
AU - Zhiping SHI
AU - Xiaowei LI
PY - 2017
DO - 10.1587/transinf.2016EDP7184
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E100-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2017
AB - Process variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.
ER -