Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests

Hiroshi IWATA; Nanami KATAYAMA; Ken'ichi YAMAGUCHI

doi:10.1587/transinf.2016FOP0007

Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests

Hiroshi IWATA, Nanami KATAYAMA, Ken'ichi YAMAGUCHI

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In accordance with Moore's law, recent design issues include shortening of time-to-market and detection of delay faults. Several studies with respect to formal techniques have examined the first issue. Using the equivalence checking, it is possible to identify whether large circuits are equivalent or not in a practical time frame. With respect to the latter issue, it is difficult to achieve 100% fault efficiency even for transition faults in full scan designs. This study involved proposing a redundant transition fault identification method using equivalence checking. The main concept of the proposed algorithm involved combining the following two known techniques, 1. modeling of a transition fault as a stuck-at fault with temporal expansion and 2. detection of a stuck-at fault by using equivalence checking tools. The experimental results indicated that the proposed redundant identification method using a formal approach achieved 100% fault efficiency for all benchmark circuits in a practical time even if a commercial ATPG tool was unable to achieve 100% fault efficiency for several circuits.

Publication: IEICE TRANSACTIONS on Information Vol.E100-D No.6 pp.1182-1189

Publication Date: 2017/06/01

Publicized: 2017/03/07

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2016FOP0007

Type of Manuscript: Special Section PAPER (Special Section on Formal Approach)

Category: Formal techniques

Authors

Hiroshi IWATA
  Kisarazu College
Nanami KATAYAMA
  Nara College
Ken'ichi YAMAGUCHI
  Nara College

Keyword

redundancy identification, transition faults, broadside scan test, formal verification and functional equivalence

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Hiroshi IWATA, Nanami KATAYAMA, Ken'ichi YAMAGUCHI, "Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests" in IEICE TRANSACTIONS on Information, vol. E100-D, no. 6, pp. 1182-1189, June 2017, doi: 10.1587/transinf.2016FOP0007.
Abstract: In accordance with Moore's law, recent design issues include shortening of time-to-market and detection of delay faults. Several studies with respect to formal techniques have examined the first issue. Using the equivalence checking, it is possible to identify whether large circuits are equivalent or not in a practical time frame. With respect to the latter issue, it is difficult to achieve 100% fault efficiency even for transition faults in full scan designs. This study involved proposing a redundant transition fault identification method using equivalence checking. The main concept of the proposed algorithm involved combining the following two known techniques, 1. modeling of a transition fault as a stuck-at fault with temporal expansion and 2. detection of a stuck-at fault by using equivalence checking tools. The experimental results indicated that the proposed redundant identification method using a formal approach achieved 100% fault efficiency for all benchmark circuits in a practical time even if a commercial ATPG tool was unable to achieve 100% fault efficiency for several circuits.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.2016FOP0007/_p

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@ARTICLE{e100-d_6_1182,
author={Hiroshi IWATA, Nanami KATAYAMA, Ken'ichi YAMAGUCHI, },
journal={IEICE TRANSACTIONS on Information},
title={Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests},
year={2017},
volume={E100-D},
number={6},
pages={1182-1189},
abstract={In accordance with Moore's law, recent design issues include shortening of time-to-market and detection of delay faults. Several studies with respect to formal techniques have examined the first issue. Using the equivalence checking, it is possible to identify whether large circuits are equivalent or not in a practical time frame. With respect to the latter issue, it is difficult to achieve 100% fault efficiency even for transition faults in full scan designs. This study involved proposing a redundant transition fault identification method using equivalence checking. The main concept of the proposed algorithm involved combining the following two known techniques, 1. modeling of a transition fault as a stuck-at fault with temporal expansion and 2. detection of a stuck-at fault by using equivalence checking tools. The experimental results indicated that the proposed redundant identification method using a formal approach achieved 100% fault efficiency for all benchmark circuits in a practical time even if a commercial ATPG tool was unable to achieve 100% fault efficiency for several circuits.},
keywords={},
doi={10.1587/transinf.2016FOP0007},
ISSN={1745-1361},
month={June},}

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TY - JOUR
TI - Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests
T2 - IEICE TRANSACTIONS on Information
SP - 1182
EP - 1189
AU - Hiroshi IWATA
AU - Nanami KATAYAMA
AU - Ken'ichi YAMAGUCHI
PY - 2017
DO - 10.1587/transinf.2016FOP0007
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E100-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2017
AB - In accordance with Moore's law, recent design issues include shortening of time-to-market and detection of delay faults. Several studies with respect to formal techniques have examined the first issue. Using the equivalence checking, it is possible to identify whether large circuits are equivalent or not in a practical time frame. With respect to the latter issue, it is difficult to achieve 100% fault efficiency even for transition faults in full scan designs. This study involved proposing a redundant transition fault identification method using equivalence checking. The main concept of the proposed algorithm involved combining the following two known techniques, 1. modeling of a transition fault as a stuck-at fault with temporal expansion and 2. detection of a stuck-at fault by using equivalence checking tools. The experimental results indicated that the proposed redundant identification method using a formal approach achieved 100% fault efficiency for all benchmark circuits in a practical time even if a commercial ATPG tool was unable to achieve 100% fault efficiency for several circuits.
ER -