Instruction set randomization (ISR) is a cost-effective obfuscation technique that modifies or enhances the relationship between instructions and machine languages. An Instruction Register File (IRF), a list of frequently used instructions, can be used for ISR by providing the way of indirect access to them. This study examines the IRF that integrates a positional register, which was proposed as a supplementary unit of the IRF, for the sake of tamper resistance. According to our evaluation, with a new design for the contents of the positional register, the measure of tamper resistance was increased by 8.2% at a maximum, which corresponds to a 32.2% increase in the size of the IRF. The number of logic elements increased by the addition of the positional register was 3.5% of its baseline processor.
Naoki FUJIEDA
Toyohashi University of Technology
Kiyohiro SATO
Toyohashi University of Technology
Ryodai IWAMOTO
Toyohashi University of Technology
Shuichi ICHIKAWA
Toyohashi University of Technology
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Naoki FUJIEDA, Kiyohiro SATO, Ryodai IWAMOTO, Shuichi ICHIKAWA, "Evaluation of Register Number Abstraction for Enhanced Instruction Register Files" in IEICE TRANSACTIONS on Information,
vol. E101-D, no. 6, pp. 1521-1531, June 2018, doi: 10.1587/transinf.2017EDP7221.
Abstract: Instruction set randomization (ISR) is a cost-effective obfuscation technique that modifies or enhances the relationship between instructions and machine languages. An Instruction Register File (IRF), a list of frequently used instructions, can be used for ISR by providing the way of indirect access to them. This study examines the IRF that integrates a positional register, which was proposed as a supplementary unit of the IRF, for the sake of tamper resistance. According to our evaluation, with a new design for the contents of the positional register, the measure of tamper resistance was increased by 8.2% at a maximum, which corresponds to a 32.2% increase in the size of the IRF. The number of logic elements increased by the addition of the positional register was 3.5% of its baseline processor.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.2017EDP7221/_p
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@ARTICLE{e101-d_6_1521,
author={Naoki FUJIEDA, Kiyohiro SATO, Ryodai IWAMOTO, Shuichi ICHIKAWA, },
journal={IEICE TRANSACTIONS on Information},
title={Evaluation of Register Number Abstraction for Enhanced Instruction Register Files},
year={2018},
volume={E101-D},
number={6},
pages={1521-1531},
abstract={Instruction set randomization (ISR) is a cost-effective obfuscation technique that modifies or enhances the relationship between instructions and machine languages. An Instruction Register File (IRF), a list of frequently used instructions, can be used for ISR by providing the way of indirect access to them. This study examines the IRF that integrates a positional register, which was proposed as a supplementary unit of the IRF, for the sake of tamper resistance. According to our evaluation, with a new design for the contents of the positional register, the measure of tamper resistance was increased by 8.2% at a maximum, which corresponds to a 32.2% increase in the size of the IRF. The number of logic elements increased by the addition of the positional register was 3.5% of its baseline processor.},
keywords={},
doi={10.1587/transinf.2017EDP7221},
ISSN={1745-1361},
month={June},}
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TY - JOUR
TI - Evaluation of Register Number Abstraction for Enhanced Instruction Register Files
T2 - IEICE TRANSACTIONS on Information
SP - 1521
EP - 1531
AU - Naoki FUJIEDA
AU - Kiyohiro SATO
AU - Ryodai IWAMOTO
AU - Shuichi ICHIKAWA
PY - 2018
DO - 10.1587/transinf.2017EDP7221
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E101-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2018
AB - Instruction set randomization (ISR) is a cost-effective obfuscation technique that modifies or enhances the relationship between instructions and machine languages. An Instruction Register File (IRF), a list of frequently used instructions, can be used for ISR by providing the way of indirect access to them. This study examines the IRF that integrates a positional register, which was proposed as a supplementary unit of the IRF, for the sake of tamper resistance. According to our evaluation, with a new design for the contents of the positional register, the measure of tamper resistance was increased by 8.2% at a maximum, which corresponds to a 32.2% increase in the size of the IRF. The number of logic elements increased by the addition of the positional register was 3.5% of its baseline processor.
ER -