Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism

Jiongyao YE; Yingtao HU; Hongfeng DING; Takahiro WATANABE

doi:10.1587/transinf.E94.D.1398

Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism

Jiongyao YE, Yingtao HU, Hongfeng DING, Takahiro WATANABE

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Power consumption has become an increasing concern in high performance microprocessor design. Especially, Instruction Cache (I-Cache) contributes a large portion of the total power consumption in a microprocessor, since it is a complex unit and is accessed very frequently. Several studies on low-power design have been presented for the power-efficient cache design. However, these techniques usually suffer from the restrictions in the traditional Instruction Fetch Unit (IFU) architectures where the fetch address needs to be sent to I-Cache once it is available. Therefore, work to reduce the power consumption is limited after the address generation and before starting an access. In this paper, we present a new power-aware IFU architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the low-power designs by eliminating the restrictions on those low-power designs of the traditional IFU. To achieve this goal, ABSA reorganizes the IFU pipeline and carefully assigns tasks for each stages so that sufficient time and information can be provided for the low-power techniques to maximize the power efficiency before starting an access. The proposed design is fully scalable and its cost is low. Compared to a conventional IFU design, simulation results show that ABSA saves about 30.3% fetch power consumption, on average. I-Cache employed by ABSA reduces both static and dynamic power consumptions about 85.63% and 66.92%, respectively. Meanwhile the performance degradation is only about 0.97%.

Publication: IEICE TRANSACTIONS on Information Vol.E94-D No.7 pp.1398-1408

Publication Date: 2011/07/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E94.D.1398

Type of Manuscript: PAPER

Category: Computer System

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Jiongyao YE, Yingtao HU, Hongfeng DING, Takahiro WATANABE, "Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism" in IEICE TRANSACTIONS on Information, vol. E94-D, no. 7, pp. 1398-1408, July 2011, doi: 10.1587/transinf.E94.D.1398.
Abstract: Power consumption has become an increasing concern in high performance microprocessor design. Especially, Instruction Cache (I-Cache) contributes a large portion of the total power consumption in a microprocessor, since it is a complex unit and is accessed very frequently. Several studies on low-power design have been presented for the power-efficient cache design. However, these techniques usually suffer from the restrictions in the traditional Instruction Fetch Unit (IFU) architectures where the fetch address needs to be sent to I-Cache once it is available. Therefore, work to reduce the power consumption is limited after the address generation and before starting an access. In this paper, we present a new power-aware IFU architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the low-power designs by eliminating the restrictions on those low-power designs of the traditional IFU. To achieve this goal, ABSA reorganizes the IFU pipeline and carefully assigns tasks for each stages so that sufficient time and information can be provided for the low-power techniques to maximize the power efficiency before starting an access. The proposed design is fully scalable and its cost is low. Compared to a conventional IFU design, simulation results show that ABSA saves about 30.3% fetch power consumption, on average. I-Cache employed by ABSA reduces both static and dynamic power consumptions about 85.63% and 66.92%, respectively. Meanwhile the performance degradation is only about 0.97%.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E94.D.1398/_p

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@ARTICLE{e94-d_7_1398,
author={Jiongyao YE, Yingtao HU, Hongfeng DING, Takahiro WATANABE, },
journal={IEICE TRANSACTIONS on Information},
title={Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism},
year={2011},
volume={E94-D},
number={7},
pages={1398-1408},
abstract={Power consumption has become an increasing concern in high performance microprocessor design. Especially, Instruction Cache (I-Cache) contributes a large portion of the total power consumption in a microprocessor, since it is a complex unit and is accessed very frequently. Several studies on low-power design have been presented for the power-efficient cache design. However, these techniques usually suffer from the restrictions in the traditional Instruction Fetch Unit (IFU) architectures where the fetch address needs to be sent to I-Cache once it is available. Therefore, work to reduce the power consumption is limited after the address generation and before starting an access. In this paper, we present a new power-aware IFU architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the low-power designs by eliminating the restrictions on those low-power designs of the traditional IFU. To achieve this goal, ABSA reorganizes the IFU pipeline and carefully assigns tasks for each stages so that sufficient time and information can be provided for the low-power techniques to maximize the power efficiency before starting an access. The proposed design is fully scalable and its cost is low. Compared to a conventional IFU design, simulation results show that ABSA saves about 30.3% fetch power consumption, on average. I-Cache employed by ABSA reduces both static and dynamic power consumptions about 85.63% and 66.92%, respectively. Meanwhile the performance degradation is only about 0.97%.},
keywords={},
doi={10.1587/transinf.E94.D.1398},
ISSN={1745-1361},
month={July},}

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TY - JOUR
TI - Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism
T2 - IEICE TRANSACTIONS on Information
SP - 1398
EP - 1408
AU - Jiongyao YE
AU - Yingtao HU
AU - Hongfeng DING
AU - Takahiro WATANABE
PY - 2011
DO - 10.1587/transinf.E94.D.1398
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2011
AB - Power consumption has become an increasing concern in high performance microprocessor design. Especially, Instruction Cache (I-Cache) contributes a large portion of the total power consumption in a microprocessor, since it is a complex unit and is accessed very frequently. Several studies on low-power design have been presented for the power-efficient cache design. However, these techniques usually suffer from the restrictions in the traditional Instruction Fetch Unit (IFU) architectures where the fetch address needs to be sent to I-Cache once it is available. Therefore, work to reduce the power consumption is limited after the address generation and before starting an access. In this paper, we present a new power-aware IFU architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the low-power designs by eliminating the restrictions on those low-power designs of the traditional IFU. To achieve this goal, ABSA reorganizes the IFU pipeline and carefully assigns tasks for each stages so that sufficient time and information can be provided for the low-power techniques to maximize the power efficiency before starting an access. The proposed design is fully scalable and its cost is low. Compared to a conventional IFU design, simulation results show that ABSA saves about 30.3% fetch power consumption, on average. I-Cache employed by ABSA reduces both static and dynamic power consumptions about 85.63% and 66.92%, respectively. Meanwhile the performance degradation is only about 0.97%.
ER -