3D-DCT Processor and Its FPGA Implementation

Yuki IKEGAKI; Toshiaki MIYAZAKI; Stanislav G. SEDUKHIN

doi:10.1587/transinf.E94.D.1409

3D-DCT Processor and Its FPGA Implementation

Yuki IKEGAKI, Toshiaki MIYAZAKI, Stanislav G. SEDUKHIN

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Conventional array processors randomly access input/coefficient data stored in memory many times during three-dimensional discrete cosine transform (3D-DCT) calculations. This causes a calculation bottleneck. In this paper, a 3D array processor dedicated to 3D-DCT is proposed. The array processor drastically reduces data swapping or replacement during the calculation and thus improves performance. The time complexity of the proposed NNN array processor is O(N) for an N³-size input data cube, and that of the 3D-DCT sequential calculation is O(N⁴). A specific I/O architecture, throughput-improved architectures, and more scalable architecture are also discussed in terms of practical implementation. Experimental results of implementation on FPGA (field-programmable gate array) suggest that our architecture provides good performance for real-time 3D-DCT calculations.

Publication: IEICE TRANSACTIONS on Information Vol.E94-D No.7 pp.1409-1418

Publication Date: 2011/07/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E94.D.1409

Type of Manuscript: PAPER

Category: Computer System

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Yuki IKEGAKI, Toshiaki MIYAZAKI, Stanislav G. SEDUKHIN, "3D-DCT Processor and Its FPGA Implementation" in IEICE TRANSACTIONS on Information, vol. E94-D, no. 7, pp. 1409-1418, July 2011, doi: 10.1587/transinf.E94.D.1409.
Abstract: Conventional array processors randomly access input/coefficient data stored in memory many times during three-dimensional discrete cosine transform (3D-DCT) calculations. This causes a calculation bottleneck. In this paper, a 3D array processor dedicated to 3D-DCT is proposed. The array processor drastically reduces data swapping or replacement during the calculation and thus improves performance. The time complexity of the proposed NNN array processor is O(N) for an N³-size input data cube, and that of the 3D-DCT sequential calculation is O(N⁴). A specific I/O architecture, throughput-improved architectures, and more scalable architecture are also discussed in terms of practical implementation. Experimental results of implementation on FPGA (field-programmable gate array) suggest that our architecture provides good performance for real-time 3D-DCT calculations.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E94.D.1409/_p

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@ARTICLE{e94-d_7_1409,
author={Yuki IKEGAKI, Toshiaki MIYAZAKI, Stanislav G. SEDUKHIN, },
journal={IEICE TRANSACTIONS on Information},
title={3D-DCT Processor and Its FPGA Implementation},
year={2011},
volume={E94-D},
number={7},
pages={1409-1418},
abstract={Conventional array processors randomly access input/coefficient data stored in memory many times during three-dimensional discrete cosine transform (3D-DCT) calculations. This causes a calculation bottleneck. In this paper, a 3D array processor dedicated to 3D-DCT is proposed. The array processor drastically reduces data swapping or replacement during the calculation and thus improves performance. The time complexity of the proposed NNN array processor is O(N) for an N³-size input data cube, and that of the 3D-DCT sequential calculation is O(N⁴). A specific I/O architecture, throughput-improved architectures, and more scalable architecture are also discussed in terms of practical implementation. Experimental results of implementation on FPGA (field-programmable gate array) suggest that our architecture provides good performance for real-time 3D-DCT calculations.},
keywords={},
doi={10.1587/transinf.E94.D.1409},
ISSN={1745-1361},
month={July},}

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TY - JOUR
TI - 3D-DCT Processor and Its FPGA Implementation
T2 - IEICE TRANSACTIONS on Information
SP - 1409
EP - 1418
AU - Yuki IKEGAKI
AU - Toshiaki MIYAZAKI
AU - Stanislav G. SEDUKHIN
PY - 2011
DO - 10.1587/transinf.E94.D.1409
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2011
AB - Conventional array processors randomly access input/coefficient data stored in memory many times during three-dimensional discrete cosine transform (3D-DCT) calculations. This causes a calculation bottleneck. In this paper, a 3D array processor dedicated to 3D-DCT is proposed. The array processor drastically reduces data swapping or replacement during the calculation and thus improves performance. The time complexity of the proposed NNN array processor is O(N) for an N³-size input data cube, and that of the 3D-DCT sequential calculation is O(N⁴). A specific I/O architecture, throughput-improved architectures, and more scalable architecture are also discussed in terms of practical implementation. Experimental results of implementation on FPGA (field-programmable gate array) suggest that our architecture provides good performance for real-time 3D-DCT calculations.
ER -