A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip

Chaochao FENG; Zhonghai LU; Axel JANTSCH; Minxuan ZHANG

doi:10.1587/transinf.E95.D.1519

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip

Chaochao FENG, Zhonghai LU, Axel JANTSCH, Minxuan ZHANG

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In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 77 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.

Publication: IEICE TRANSACTIONS on Information Vol.E95-D No.5 pp.1519-1522

Publication Date: 2012/05/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E95.D.1519

Type of Manuscript: LETTER

Category: Computer System

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Chaochao FENG, Zhonghai LU, Axel JANTSCH, Minxuan ZHANG, "A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip" in IEICE TRANSACTIONS on Information, vol. E95-D, no. 5, pp. 1519-1522, May 2012, doi: 10.1587/transinf.E95.D.1519.
Abstract: In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 77 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E95.D.1519/_p

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@ARTICLE{e95-d_5_1519,
author={Chaochao FENG, Zhonghai LU, Axel JANTSCH, Minxuan ZHANG, },
journal={IEICE TRANSACTIONS on Information},
title={A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip},
year={2012},
volume={E95-D},
number={5},
pages={1519-1522},
abstract={In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 77 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.},
keywords={},
doi={10.1587/transinf.E95.D.1519},
ISSN={1745-1361},
month={May},}

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TY - JOUR
TI - A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip
T2 - IEICE TRANSACTIONS on Information
SP - 1519
EP - 1522
AU - Chaochao FENG
AU - Zhonghai LU
AU - Axel JANTSCH
AU - Minxuan ZHANG
PY - 2012
DO - 10.1587/transinf.E95.D.1519
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2012
AB - In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 77 crossbar to achieve the frequency of 1.25 GHz in TSMC 65 nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.
ER -