Design and Implementation of a Handshake Join Architecture on FPGA

Yasin OGE; Takefumi MIYOSHI; Hideyuki KAWASHIMA; Tsutomu YOSHINAGA

doi:10.1587/transinf.E95.D.2919

Design and Implementation of a Handshake Join Architecture on FPGA

Yasin OGE, Takefumi MIYOSHI, Hideyuki KAWASHIMA, Tsutomu YOSHINAGA

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A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.

Publication: IEICE TRANSACTIONS on Information Vol.E95-D No.12 pp.2919-2927

Publication Date: 2012/12/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E95.D.2919

Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)

Category: Computer Architecture

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Yasin OGE, Takefumi MIYOSHI, Hideyuki KAWASHIMA, Tsutomu YOSHINAGA, "Design and Implementation of a Handshake Join Architecture on FPGA" in IEICE TRANSACTIONS on Information, vol. E95-D, no. 12, pp. 2919-2927, December 2012, doi: 10.1587/transinf.E95.D.2919.
Abstract: A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E95.D.2919/_p

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@ARTICLE{e95-d_12_2919,
author={Yasin OGE, Takefumi MIYOSHI, Hideyuki KAWASHIMA, Tsutomu YOSHINAGA, },
journal={IEICE TRANSACTIONS on Information},
title={Design and Implementation of a Handshake Join Architecture on FPGA},
year={2012},
volume={E95-D},
number={12},
pages={2919-2927},
abstract={A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.},
keywords={},
doi={10.1587/transinf.E95.D.2919},
ISSN={1745-1361},
month={December},}

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TY - JOUR
TI - Design and Implementation of a Handshake Join Architecture on FPGA
T2 - IEICE TRANSACTIONS on Information
SP - 2919
EP - 2927
AU - Yasin OGE
AU - Takefumi MIYOSHI
AU - Hideyuki KAWASHIMA
AU - Tsutomu YOSHINAGA
PY - 2012
DO - 10.1587/transinf.E95.D.2919
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2012
AB - A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.
ER -