Using Cacheline Reuse Characteristics for Prefetcher Throttling

Hidetsugu IRIE; Takefumi MIYOSHI; Goki HONJO; Kei HIRAKI; Tsutomu YOSHINAGA

doi:10.1587/transinf.E95.D.2928

Using Cacheline Reuse Characteristics for Prefetcher Throttling

Hidetsugu IRIE, Takefumi MIYOSHI, Goki HONJO, Kei HIRAKI, Tsutomu YOSHINAGA

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One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs' working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+), which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256 KB LLC, 1.8% over the latest prefetcher throttling, and 0.5% over our previous CCCPO. Moreover, it showed superior stability compared to related works, while lowering the hardware cost.

Publication: IEICE TRANSACTIONS on Information Vol.E95-D No.12 pp.2928-2938

Publication Date: 2012/12/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E95.D.2928

Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)

Category: Computer Architecture

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Hidetsugu IRIE, Takefumi MIYOSHI, Goki HONJO, Kei HIRAKI, Tsutomu YOSHINAGA, "Using Cacheline Reuse Characteristics for Prefetcher Throttling" in IEICE TRANSACTIONS on Information, vol. E95-D, no. 12, pp. 2928-2938, December 2012, doi: 10.1587/transinf.E95.D.2928.
Abstract: One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs' working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+), which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256 KB LLC, 1.8% over the latest prefetcher throttling, and 0.5% over our previous CCCPO. Moreover, it showed superior stability compared to related works, while lowering the hardware cost.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E95.D.2928/_p

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@ARTICLE{e95-d_12_2928,
author={Hidetsugu IRIE, Takefumi MIYOSHI, Goki HONJO, Kei HIRAKI, Tsutomu YOSHINAGA, },
journal={IEICE TRANSACTIONS on Information},
title={Using Cacheline Reuse Characteristics for Prefetcher Throttling},
year={2012},
volume={E95-D},
number={12},
pages={2928-2938},
abstract={One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs' working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+), which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256 KB LLC, 1.8% over the latest prefetcher throttling, and 0.5% over our previous CCCPO. Moreover, it showed superior stability compared to related works, while lowering the hardware cost.},
keywords={},
doi={10.1587/transinf.E95.D.2928},
ISSN={1745-1361},
month={December},}

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TY - JOUR
TI - Using Cacheline Reuse Characteristics for Prefetcher Throttling
T2 - IEICE TRANSACTIONS on Information
SP - 2928
EP - 2938
AU - Hidetsugu IRIE
AU - Takefumi MIYOSHI
AU - Goki HONJO
AU - Kei HIRAKI
AU - Tsutomu YOSHINAGA
PY - 2012
DO - 10.1587/transinf.E95.D.2928
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2012
AB - One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs' working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+), which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256 KB LLC, 1.8% over the latest prefetcher throttling, and 0.5% over our previous CCCPO. Moreover, it showed superior stability compared to related works, while lowering the hardware cost.
ER -