In this paper, a hybrid parallel implementation of inverse matrix computation using SMW formula is proposed. By aggregating the memory bandwidth in the hybrid parallel implementation, the bottleneck due to the memory bandwidth limitation in the authors previous multicore implementation has been dissolved. More than 8 times of speed up is also achieved with dual-core 8-nodes implementation which leads more than 20 simulation steps per second, or near real-time performance.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Shotaro IWANAGA, Shinji FUKUMA, Shin-ichiro MORI, "Hybrid Parallel Implementation of Inverse Matrix Computation by SMW Formula for Interactive Simulation" in IEICE TRANSACTIONS on Information,
vol. E95-D, no. 12, pp. 2952-2953, December 2012, doi: 10.1587/transinf.E95.D.2952.
Abstract: In this paper, a hybrid parallel implementation of inverse matrix computation using SMW formula is proposed. By aggregating the memory bandwidth in the hybrid parallel implementation, the bottleneck due to the memory bandwidth limitation in the authors previous multicore implementation has been dissolved. More than 8 times of speed up is also achieved with dual-core 8-nodes implementation which leads more than 20 simulation steps per second, or near real-time performance.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E95.D.2952/_p
Copy
@ARTICLE{e95-d_12_2952,
author={Shotaro IWANAGA, Shinji FUKUMA, Shin-ichiro MORI, },
journal={IEICE TRANSACTIONS on Information},
title={Hybrid Parallel Implementation of Inverse Matrix Computation by SMW Formula for Interactive Simulation},
year={2012},
volume={E95-D},
number={12},
pages={2952-2953},
abstract={In this paper, a hybrid parallel implementation of inverse matrix computation using SMW formula is proposed. By aggregating the memory bandwidth in the hybrid parallel implementation, the bottleneck due to the memory bandwidth limitation in the authors previous multicore implementation has been dissolved. More than 8 times of speed up is also achieved with dual-core 8-nodes implementation which leads more than 20 simulation steps per second, or near real-time performance.},
keywords={},
doi={10.1587/transinf.E95.D.2952},
ISSN={1745-1361},
month={December},}
Copy
TY - JOUR
TI - Hybrid Parallel Implementation of Inverse Matrix Computation by SMW Formula for Interactive Simulation
T2 - IEICE TRANSACTIONS on Information
SP - 2952
EP - 2953
AU - Shotaro IWANAGA
AU - Shinji FUKUMA
AU - Shin-ichiro MORI
PY - 2012
DO - 10.1587/transinf.E95.D.2952
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2012
AB - In this paper, a hybrid parallel implementation of inverse matrix computation using SMW formula is proposed. By aggregating the memory bandwidth in the hybrid parallel implementation, the bottleneck due to the memory bandwidth limitation in the authors previous multicore implementation has been dissolved. More than 8 times of speed up is also achieved with dual-core 8-nodes implementation which leads more than 20 simulation steps per second, or near real-time performance.
ER -