A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

Krzysztof JOZWIK; Hiroyuki TOMIYAMA; Shinya HONDA; Hiroaki TAKADA

doi:10.1587/transinf.E95.D.345

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

Krzysztof JOZWIK, Hiroyuki TOMIYAMA, Shinya HONDA, Hiroaki TAKADA

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Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

Publication: IEICE TRANSACTIONS on Information Vol.E95-D No.2 pp.345-353

Publication Date: 2012/02/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E95.D.345

Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)

Category: Design Methodology

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Krzysztof JOZWIK, Hiroyuki TOMIYAMA, Shinya HONDA, Hiroaki TAKADA, "A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs" in IEICE TRANSACTIONS on Information, vol. E95-D, no. 2, pp. 345-353, February 2012, doi: 10.1587/transinf.E95.D.345.
Abstract: Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E95.D.345/_p

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@ARTICLE{e95-d_2_345,
author={Krzysztof JOZWIK, Hiroyuki TOMIYAMA, Shinya HONDA, Hiroaki TAKADA, },
journal={IEICE TRANSACTIONS on Information},
title={A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs},
year={2012},
volume={E95-D},
number={2},
pages={345-353},
abstract={Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.},
keywords={},
doi={10.1587/transinf.E95.D.345},
ISSN={1745-1361},
month={February},}

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TY - JOUR
TI - A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs
T2 - IEICE TRANSACTIONS on Information
SP - 345
EP - 353
AU - Krzysztof JOZWIK
AU - Hiroyuki TOMIYAMA
AU - Shinya HONDA
AU - Hiroaki TAKADA
PY - 2012
DO - 10.1587/transinf.E95.D.345
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2012
AB - Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.
ER -