Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

Xinning LIU; Chen MEI; Peng CAO; Min ZHU; Longxing SHI

doi:10.1587/transinf.E95.D.374

Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

Xinning LIU, Chen MEI, Peng CAO, Min ZHU, Longxing SHI

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This paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), a dynamically coarse grain reconfigurable architecture. REMUS-II consists of a µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used to speeds up control-intensive tasks and data-intensive tasks respectively. The parallel computing capability and flexibility of REMUS-II makes itself an excellent candidate to process multimedia applications, which require a large amount of memory accesses. In this paper, we specifically optimize the data flow to deal with those performance-hazard and energy-hungry memory accessing in order to meet the bandwidth requirement of parallel computing. The RPU internal memory could work in multiple modes, like 2D-access mode and transformation mode, according to different multimedia access patterns. This novel design can improve the performance up to 26% compared to traditional on-chip memory. Meanwhile, the block buffer is implemented to optimize the off-chip data flow through reducing off-chip memory accesses, which reducing up to 43% compared to direct DDR access. Based on RTL simulation, REMUS-II can achieve 1080p@30 fps of H.264 High Profile@ Level 4 and High Level MPEG2 at 200 MHz clock frequency. The REMUS-II is implemented into 23.7 mm² silicon on TSMC 65 nm logic process with a 400 MHz maximum working frequency.

Publication: IEICE TRANSACTIONS on Information Vol.E95-D No.2 pp.374-382

Publication Date: 2012/02/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E95.D.374

Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)

Category: Design Methodology

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Xinning LIU, Chen MEI, Peng CAO, Min ZHU, Longxing SHI, "Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications" in IEICE TRANSACTIONS on Information, vol. E95-D, no. 2, pp. 374-382, February 2012, doi: 10.1587/transinf.E95.D.374.
Abstract: This paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), a dynamically coarse grain reconfigurable architecture. REMUS-II consists of a µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used to speeds up control-intensive tasks and data-intensive tasks respectively. The parallel computing capability and flexibility of REMUS-II makes itself an excellent candidate to process multimedia applications, which require a large amount of memory accesses. In this paper, we specifically optimize the data flow to deal with those performance-hazard and energy-hungry memory accessing in order to meet the bandwidth requirement of parallel computing. The RPU internal memory could work in multiple modes, like 2D-access mode and transformation mode, according to different multimedia access patterns. This novel design can improve the performance up to 26% compared to traditional on-chip memory. Meanwhile, the block buffer is implemented to optimize the off-chip data flow through reducing off-chip memory accesses, which reducing up to 43% compared to direct DDR access. Based on RTL simulation, REMUS-II can achieve 1080p@30 fps of H.264 High Profile@ Level 4 and High Level MPEG2 at 200 MHz clock frequency. The REMUS-II is implemented into 23.7 mm² silicon on TSMC 65 nm logic process with a 400 MHz maximum working frequency.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E95.D.374/_p

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@ARTICLE{e95-d_2_374,
author={Xinning LIU, Chen MEI, Peng CAO, Min ZHU, Longxing SHI, },
journal={IEICE TRANSACTIONS on Information},
title={Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications},
year={2012},
volume={E95-D},
number={2},
pages={374-382},
abstract={This paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), a dynamically coarse grain reconfigurable architecture. REMUS-II consists of a µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used to speeds up control-intensive tasks and data-intensive tasks respectively. The parallel computing capability and flexibility of REMUS-II makes itself an excellent candidate to process multimedia applications, which require a large amount of memory accesses. In this paper, we specifically optimize the data flow to deal with those performance-hazard and energy-hungry memory accessing in order to meet the bandwidth requirement of parallel computing. The RPU internal memory could work in multiple modes, like 2D-access mode and transformation mode, according to different multimedia access patterns. This novel design can improve the performance up to 26% compared to traditional on-chip memory. Meanwhile, the block buffer is implemented to optimize the off-chip data flow through reducing off-chip memory accesses, which reducing up to 43% compared to direct DDR access. Based on RTL simulation, REMUS-II can achieve 1080p@30 fps of H.264 High Profile@ Level 4 and High Level MPEG2 at 200 MHz clock frequency. The REMUS-II is implemented into 23.7 mm² silicon on TSMC 65 nm logic process with a 400 MHz maximum working frequency.},
keywords={},
doi={10.1587/transinf.E95.D.374},
ISSN={1745-1361},
month={February},}

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TY - JOUR
TI - Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications
T2 - IEICE TRANSACTIONS on Information
SP - 374
EP - 382
AU - Xinning LIU
AU - Chen MEI
AU - Peng CAO
AU - Min ZHU
AU - Longxing SHI
PY - 2012
DO - 10.1587/transinf.E95.D.374
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2012
AB - This paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), a dynamically coarse grain reconfigurable architecture. REMUS-II consists of a µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used to speeds up control-intensive tasks and data-intensive tasks respectively. The parallel computing capability and flexibility of REMUS-II makes itself an excellent candidate to process multimedia applications, which require a large amount of memory accesses. In this paper, we specifically optimize the data flow to deal with those performance-hazard and energy-hungry memory accessing in order to meet the bandwidth requirement of parallel computing. The RPU internal memory could work in multiple modes, like 2D-access mode and transformation mode, according to different multimedia access patterns. This novel design can improve the performance up to 26% compared to traditional on-chip memory. Meanwhile, the block buffer is implemented to optimize the off-chip data flow through reducing off-chip memory accesses, which reducing up to 43% compared to direct DDR access. Based on RTL simulation, REMUS-II can achieve 1080p@30 fps of H.264 High Profile@ Level 4 and High Level MPEG2 at 200 MHz clock frequency. The REMUS-II is implemented into 23.7 mm² silicon on TSMC 65 nm logic process with a 400 MHz maximum working frequency.
ER -