FPGA Design Framework Combined with Commercial VLSI CAD

Qian ZHAO; Kazuki INOUE; Motoki AMAGASAKI; Masahiro IIDA; Morihiro KUGA; Toshinori SUEYOSHI

doi:10.1587/transinf.E96.D.1602

FPGA Design Framework Combined with Commercial VLSI CAD

Qian ZHAO, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI

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The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.

Publication: IEICE TRANSACTIONS on Information Vol.E96-D No.8 pp.1602-1612

Publication Date: 2013/08/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E96.D.1602

Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)

Category: Design Methodology

Authors

Qian ZHAO
  Kumamoto University
Kazuki INOUE
  Kumamoto University
Motoki AMAGASAKI
  Kumamoto University
Masahiro IIDA
  Kumamoto University
Morihiro KUGA
  Kumamoto University
Toshinori SUEYOSHI
  Kumamoto University

Keyword

FPGA, CAD, routing

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Qian ZHAO, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, "FPGA Design Framework Combined with Commercial VLSI CAD" in IEICE TRANSACTIONS on Information, vol. E96-D, no. 8, pp. 1602-1612, August 2013, doi: 10.1587/transinf.E96.D.1602.
Abstract: The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E96.D.1602/_p

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@ARTICLE{e96-d_8_1602,
author={Qian ZHAO, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Information},
title={FPGA Design Framework Combined with Commercial VLSI CAD},
year={2013},
volume={E96-D},
number={8},
pages={1602-1612},
abstract={The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.},
keywords={},
doi={10.1587/transinf.E96.D.1602},
ISSN={1745-1361},
month={August},}

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TY - JOUR
TI - FPGA Design Framework Combined with Commercial VLSI CAD
T2 - IEICE TRANSACTIONS on Information
SP - 1602
EP - 1612
AU - Qian ZHAO
AU - Kazuki INOUE
AU - Motoki AMAGASAKI
AU - Masahiro IIDA
AU - Morihiro KUGA
AU - Toshinori SUEYOSHI
PY - 2013
DO - 10.1587/transinf.E96.D.1602
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2013
AB - The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.
ER -