Power consumption has become a critical factor for embedded systems, especially for battery powered ones. Caches in these systems consume a large portion of the whole chip power. Embedded systems usually adopt set-associative caches to get better performance. However, parallel accessed cache ways incur more energy dissipation. This paper proposed a region-based way-partitioning scheme to reduce cache way access, and without sacrificing performance, to reduce the cache power consumption. The stack accesses and non-stack accesses are isolated and redirected to different ways of the L1 data cache. Under way-partitioning, cache way accesses are reduced, as well as the memory reference interference. Experimental results show that the proposed approach could save around 27.5% of L1 data cache energy on average, without significant performance degradation.
Zhong ZHENG
National University of Defense Technology (NUDT)
Zhiying WANG
National University of Defense Technology (NUDT)
Li SHEN
National University of Defense Technology (NUDT)
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Zhong ZHENG, Zhiying WANG, Li SHEN, "Region-Based Way-Partitioning on L1 Data Cache for Low Power" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 11, pp. 2466-2469, November 2013, doi: 10.1587/transinf.E96.D.2466.
Abstract: Power consumption has become a critical factor for embedded systems, especially for battery powered ones. Caches in these systems consume a large portion of the whole chip power. Embedded systems usually adopt set-associative caches to get better performance. However, parallel accessed cache ways incur more energy dissipation. This paper proposed a region-based way-partitioning scheme to reduce cache way access, and without sacrificing performance, to reduce the cache power consumption. The stack accesses and non-stack accesses are isolated and redirected to different ways of the L1 data cache. Under way-partitioning, cache way accesses are reduced, as well as the memory reference interference. Experimental results show that the proposed approach could save around 27.5% of L1 data cache energy on average, without significant performance degradation.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E96.D.2466/_p
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@ARTICLE{e96-d_11_2466,
author={Zhong ZHENG, Zhiying WANG, Li SHEN, },
journal={IEICE TRANSACTIONS on Information},
title={Region-Based Way-Partitioning on L1 Data Cache for Low Power},
year={2013},
volume={E96-D},
number={11},
pages={2466-2469},
abstract={Power consumption has become a critical factor for embedded systems, especially for battery powered ones. Caches in these systems consume a large portion of the whole chip power. Embedded systems usually adopt set-associative caches to get better performance. However, parallel accessed cache ways incur more energy dissipation. This paper proposed a region-based way-partitioning scheme to reduce cache way access, and without sacrificing performance, to reduce the cache power consumption. The stack accesses and non-stack accesses are isolated and redirected to different ways of the L1 data cache. Under way-partitioning, cache way accesses are reduced, as well as the memory reference interference. Experimental results show that the proposed approach could save around 27.5% of L1 data cache energy on average, without significant performance degradation.},
keywords={},
doi={10.1587/transinf.E96.D.2466},
ISSN={1745-1361},
month={November},}
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TY - JOUR
TI - Region-Based Way-Partitioning on L1 Data Cache for Low Power
T2 - IEICE TRANSACTIONS on Information
SP - 2466
EP - 2469
AU - Zhong ZHENG
AU - Zhiying WANG
AU - Li SHEN
PY - 2013
DO - 10.1587/transinf.E96.D.2466
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2013
AB - Power consumption has become a critical factor for embedded systems, especially for battery powered ones. Caches in these systems consume a large portion of the whole chip power. Embedded systems usually adopt set-associative caches to get better performance. However, parallel accessed cache ways incur more energy dissipation. This paper proposed a region-based way-partitioning scheme to reduce cache way access, and without sacrificing performance, to reduce the cache power consumption. The stack accesses and non-stack accesses are isolated and redirected to different ways of the L1 data cache. Under way-partitioning, cache way accesses are reduced, as well as the memory reference interference. Experimental results show that the proposed approach could save around 27.5% of L1 data cache energy on average, without significant performance degradation.
ER -