Region-Based Way-Partitioning on L1 Data Cache for Low Power

Zhong ZHENG, Zhiying WANG, Li SHEN

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Summary :

Power consumption has become a critical factor for embedded systems, especially for battery powered ones. Caches in these systems consume a large portion of the whole chip power. Embedded systems usually adopt set-associative caches to get better performance. However, parallel accessed cache ways incur more energy dissipation. This paper proposed a region-based way-partitioning scheme to reduce cache way access, and without sacrificing performance, to reduce the cache power consumption. The stack accesses and non-stack accesses are isolated and redirected to different ways of the L1 data cache. Under way-partitioning, cache way accesses are reduced, as well as the memory reference interference. Experimental results show that the proposed approach could save around 27.5% of L1 data cache energy on average, without significant performance degradation.

Publication
IEICE TRANSACTIONS on Information Vol.E96-D No.11 pp.2466-2469
Publication Date
2013/11/01
Publicized
Online ISSN
1745-1361
DOI
10.1587/transinf.E96.D.2466
Type of Manuscript
LETTER
Category
Computer System

Authors

Zhong ZHENG
  National University of Defense Technology (NUDT)
Zhiying WANG
  National University of Defense Technology (NUDT)
Li SHEN
  National University of Defense Technology (NUDT)

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