Architecture and Implementation of a Reduced EPIC Processor

Jun GAO; Minxuan ZHANG; Zuocheng XING; Chaochao FENG

doi:10.1587/transinf.E96.D.9

Architecture and Implementation of a Reduced EPIC Processor

Jun GAO, Minxuan ZHANG, Zuocheng XING, Chaochao FENG

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This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor. The REPICP based on EPIC architecture overcomes the disadvantages of hardware-based superscalar and software-based Very Long Instruction Word (VLIW) and utilizes the cooperation of compiler and hardware to enhance Instruction-Level Parallelism (ILP). In REPICP, we propose the Optimized Lock-Step execution Model (OLSM) and instruction control pipeline method. We also propose reduced innovative methods to optimize the design. The REPICP is fabricated in Artisan 0.13 µm Nominal 1P8M process with 57 M transistors. The die size of the REPICP is 100 mm² (1010), and consumes only 12 W power when running at 300 MHz.

Publication: IEICE TRANSACTIONS on Information Vol.E96-D No.1 pp.9-18

Publication Date: 2013/01/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E96.D.9

Type of Manuscript: PAPER

Category: Computer System

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Jun GAO, Minxuan ZHANG, Zuocheng XING, Chaochao FENG, "Architecture and Implementation of a Reduced EPIC Processor" in IEICE TRANSACTIONS on Information, vol. E96-D, no. 1, pp. 9-18, January 2013, doi: 10.1587/transinf.E96.D.9.
Abstract: This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor. The REPICP based on EPIC architecture overcomes the disadvantages of hardware-based superscalar and software-based Very Long Instruction Word (VLIW) and utilizes the cooperation of compiler and hardware to enhance Instruction-Level Parallelism (ILP). In REPICP, we propose the Optimized Lock-Step execution Model (OLSM) and instruction control pipeline method. We also propose reduced innovative methods to optimize the design. The REPICP is fabricated in Artisan 0.13 µm Nominal 1P8M process with 57 M transistors. The die size of the REPICP is 100 mm² (1010), and consumes only 12 W power when running at 300 MHz.
URL: https://globals.ieice.org/en_transactions/information/10.1587/transinf.E96.D.9/_p

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@ARTICLE{e96-d_1_9,
author={Jun GAO, Minxuan ZHANG, Zuocheng XING, Chaochao FENG, },
journal={IEICE TRANSACTIONS on Information},
title={Architecture and Implementation of a Reduced EPIC Processor},
year={2013},
volume={E96-D},
number={1},
pages={9-18},
abstract={This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor. The REPICP based on EPIC architecture overcomes the disadvantages of hardware-based superscalar and software-based Very Long Instruction Word (VLIW) and utilizes the cooperation of compiler and hardware to enhance Instruction-Level Parallelism (ILP). In REPICP, we propose the Optimized Lock-Step execution Model (OLSM) and instruction control pipeline method. We also propose reduced innovative methods to optimize the design. The REPICP is fabricated in Artisan 0.13 µm Nominal 1P8M process with 57 M transistors. The die size of the REPICP is 100 mm² (1010), and consumes only 12 W power when running at 300 MHz.},
keywords={},
doi={10.1587/transinf.E96.D.9},
ISSN={1745-1361},
month={January},}

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TY - JOUR
TI - Architecture and Implementation of a Reduced EPIC Processor
T2 - IEICE TRANSACTIONS on Information
SP - 9
EP - 18
AU - Jun GAO
AU - Minxuan ZHANG
AU - Zuocheng XING
AU - Chaochao FENG
PY - 2013
DO - 10.1587/transinf.E96.D.9
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2013
AB - This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor. The REPICP based on EPIC architecture overcomes the disadvantages of hardware-based superscalar and software-based Very Long Instruction Word (VLIW) and utilizes the cooperation of compiler and hardware to enhance Instruction-Level Parallelism (ILP). In REPICP, we propose the Optimized Lock-Step execution Model (OLSM) and instruction control pipeline method. We also propose reduced innovative methods to optimize the design. The REPICP is fabricated in Artisan 0.13 µm Nominal 1P8M process with 57 M transistors. The die size of the REPICP is 100 mm² (1010), and consumes only 12 W power when running at 300 MHz.
ER -