Fault-Tolerant Arithmetic Logic Unit Using Parity-Based Codes

Eiji FUJIWARA; Kazuo HARUTA

Fault-Tolerant Arithmetic Logic Unit Using Parity-Based Codes

Eiji FUJIWARA, Kazuo HARUTA

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Use of parity-based codes in computer systems can provide a cost-effective error detection and correction. Excellent parity-based main memory codes, such as odd-weight-column SEC-DED (Single bit Error Correcting Double bit Error Detecting) codes, can be used to arithmetic logic unit (ALU) by the technique proposed in this paper. They are more economical and better suited for a byte-sliced design of fault-tolerant computer systems than residue codes and triplication organization.

Publication: IEICE TRANSACTIONS on transactions Vol.E64-E No.10 pp.653-660

Publication Date: 1981/10/25

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Type of Manuscript: PAPER

Category: Computers

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Eiji FUJIWARA
Kazuo HARUTA

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Eiji FUJIWARA, Kazuo HARUTA, "Fault-Tolerant Arithmetic Logic Unit Using Parity-Based Codes" in IEICE TRANSACTIONS on transactions, vol. E64-E, no. 10, pp. 653-660, October 1981, doi: .
Abstract: Use of parity-based codes in computer systems can provide a cost-effective error detection and correction. Excellent parity-based main memory codes, such as odd-weight-column SEC-DED (Single bit Error Correcting Double bit Error Detecting) codes, can be used to arithmetic logic unit (ALU) by the technique proposed in this paper. They are more economical and better suited for a byte-sliced design of fault-tolerant computer systems than residue codes and triplication organization.
URL: https://globals.ieice.org/en_transactions/transactions/10.1587/e64-e_10_653/_p

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@ARTICLE{e64-e_10_653,
author={Eiji FUJIWARA, Kazuo HARUTA, },
journal={IEICE TRANSACTIONS on transactions},
title={Fault-Tolerant Arithmetic Logic Unit Using Parity-Based Codes},
year={1981},
volume={E64-E},
number={10},
pages={653-660},
abstract={Use of parity-based codes in computer systems can provide a cost-effective error detection and correction. Excellent parity-based main memory codes, such as odd-weight-column SEC-DED (Single bit Error Correcting Double bit Error Detecting) codes, can be used to arithmetic logic unit (ALU) by the technique proposed in this paper. They are more economical and better suited for a byte-sliced design of fault-tolerant computer systems than residue codes and triplication organization.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Fault-Tolerant Arithmetic Logic Unit Using Parity-Based Codes
T2 - IEICE TRANSACTIONS on transactions
SP - 653
EP - 660
AU - Eiji FUJIWARA
AU - Kazuo HARUTA
PY - 1981
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E64-E
IS - 10
JA - IEICE TRANSACTIONS on transactions
Y1 - October 1981
AB - Use of parity-based codes in computer systems can provide a cost-effective error detection and correction. Excellent parity-based main memory codes, such as odd-weight-column SEC-DED (Single bit Error Correcting Double bit Error Detecting) codes, can be used to arithmetic logic unit (ALU) by the technique proposed in this paper. They are more economical and better suited for a byte-sliced design of fault-tolerant computer systems than residue codes and triplication organization.
ER -