Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method

Hideki ASAI; Atsushi KUMITA

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Hideki ASAI, Atsushi KUMITA, "Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method" in IEICE TRANSACTIONS on transactions, vol. E71-E, no. 10, pp. 962-964, October 1988, doi: .
Abstract: Recently, several tearing methods have been studied for efficient analysis of the large scale network. In this paper, we apply the gate level node tearing method to bipolar circuit simulation by direct method and show the concrete estimation of its availability.
URL: https://globals.ieice.org/en_transactions/transactions/10.1587/e71-e_10_962/_p

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@ARTICLE{e71-e_10_962,
author={Hideki ASAI, Atsushi KUMITA, },
journal={IEICE TRANSACTIONS on transactions},
title={Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method},
year={1988},
volume={E71-E},
number={10},
pages={962-964},
abstract={Recently, several tearing methods have been studied for efficient analysis of the large scale network. In this paper, we apply the gate level node tearing method to bipolar circuit simulation by direct method and show the concrete estimation of its availability.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method
T2 - IEICE TRANSACTIONS on transactions
SP - 962
EP - 964
AU - Hideki ASAI
AU - Atsushi KUMITA
PY - 1988
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E71-E
IS - 10
JA - IEICE TRANSACTIONS on transactions
Y1 - October 1988
AB - Recently, several tearing methods have been studied for efficient analysis of the large scale network. In this paper, we apply the gate level node tearing method to bipolar circuit simulation by direct method and show the concrete estimation of its availability.
ER -