A Floorplanning Scheme of VLSI Design

Takashi KAMBE; Tuneo TOMITA

A Floorplanning Scheme of VLSI Design

Takashi KAMBE, Tuneo TOMITA

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This paper describes a top-down floorplanning scheme for VLSI chips which is constructed on the basis of a heuristic algorithm and an interactive placement improvement process in conjunction with a knowledge-based expert systems approach. This scheme determines not only relative positions of the modules to be mounted on a chip but also shapes and areas of modules, according to specifications imposed on the total chip area, aspect ratios of modules, wire lengths of specific nets, electrical performances, and so forth. Several implementation results are also shown to reveal the performance of this scheme.

Publication: IEICE TRANSACTIONS on transactions Vol.E71-E No.12 pp.1236-1242

Publication Date: 1988/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on CAS Karuizawa Workshop)

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Takashi KAMBE
Tuneo TOMITA

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Takashi KAMBE, Tuneo TOMITA, "A Floorplanning Scheme of VLSI Design" in IEICE TRANSACTIONS on transactions, vol. E71-E, no. 12, pp. 1236-1242, December 1988, doi: .
Abstract: This paper describes a top-down floorplanning scheme for VLSI chips which is constructed on the basis of a heuristic algorithm and an interactive placement improvement process in conjunction with a knowledge-based expert systems approach. This scheme determines not only relative positions of the modules to be mounted on a chip but also shapes and areas of modules, according to specifications imposed on the total chip area, aspect ratios of modules, wire lengths of specific nets, electrical performances, and so forth. Several implementation results are also shown to reveal the performance of this scheme.
URL: https://globals.ieice.org/en_transactions/transactions/10.1587/e71-e_12_1236/_p

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@ARTICLE{e71-e_12_1236,
author={Takashi KAMBE, Tuneo TOMITA, },
journal={IEICE TRANSACTIONS on transactions},
title={A Floorplanning Scheme of VLSI Design},
year={1988},
volume={E71-E},
number={12},
pages={1236-1242},
abstract={This paper describes a top-down floorplanning scheme for VLSI chips which is constructed on the basis of a heuristic algorithm and an interactive placement improvement process in conjunction with a knowledge-based expert systems approach. This scheme determines not only relative positions of the modules to be mounted on a chip but also shapes and areas of modules, according to specifications imposed on the total chip area, aspect ratios of modules, wire lengths of specific nets, electrical performances, and so forth. Several implementation results are also shown to reveal the performance of this scheme.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Floorplanning Scheme of VLSI Design
T2 - IEICE TRANSACTIONS on transactions
SP - 1236
EP - 1242
AU - Takashi KAMBE
AU - Tuneo TOMITA
PY - 1988
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E71-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1988
AB - This paper describes a top-down floorplanning scheme for VLSI chips which is constructed on the basis of a heuristic algorithm and an interactive placement improvement process in conjunction with a knowledge-based expert systems approach. This scheme determines not only relative positions of the modules to be mounted on a chip but also shapes and areas of modules, according to specifications imposed on the total chip area, aspect ratios of modules, wire lengths of specific nets, electrical performances, and so forth. Several implementation results are also shown to reveal the performance of this scheme.
ER -