Fast Test Pattern Generation Using a Multiprocessor System

Hideo FUJIWARA; Akira MOTOHARA

Fast Test Pattern Generation Using a Multiprocessor System

Hideo FUJIWARA, Akira MOTOHARA

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An approach for parallel processing of test-pattern generation for combinational circuits is described. In general, difficulty in test-pattern generation lies in two points; how to deal with a large number of faults, and what to do with faults that are hard to generate their test patterns. These problems can be resolved in a parallel-processing environment on a variable number of processors. Test-pattern generation is shown to be a good application of parallel processing techniques. The proposed method has been implemented on a multi-microcomputer system called LINKS-1 in order to estimate its performance. The results show that the proposed parallel processing method can get a high parallelism and achieve a high degree of acceleration of test-pattern generation.

Publication: IEICE TRANSACTIONS on transactions Vol.E71-E No.4 pp.441-447

Publication Date: 1988/04/25

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Type of Manuscript: PAPER

Category: Fault Tolerant Computing

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Hideo FUJIWARA
Akira MOTOHARA

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Hideo FUJIWARA, Akira MOTOHARA, "Fast Test Pattern Generation Using a Multiprocessor System" in IEICE TRANSACTIONS on transactions, vol. E71-E, no. 4, pp. 441-447, April 1988, doi: .
Abstract: An approach for parallel processing of test-pattern generation for combinational circuits is described. In general, difficulty in test-pattern generation lies in two points; how to deal with a large number of faults, and what to do with faults that are hard to generate their test patterns. These problems can be resolved in a parallel-processing environment on a variable number of processors. Test-pattern generation is shown to be a good application of parallel processing techniques. The proposed method has been implemented on a multi-microcomputer system called LINKS-1 in order to estimate its performance. The results show that the proposed parallel processing method can get a high parallelism and achieve a high degree of acceleration of test-pattern generation.
URL: https://globals.ieice.org/en_transactions/transactions/10.1587/e71-e_4_441/_p

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@ARTICLE{e71-e_4_441,
author={Hideo FUJIWARA, Akira MOTOHARA, },
journal={IEICE TRANSACTIONS on transactions},
title={Fast Test Pattern Generation Using a Multiprocessor System},
year={1988},
volume={E71-E},
number={4},
pages={441-447},
abstract={An approach for parallel processing of test-pattern generation for combinational circuits is described. In general, difficulty in test-pattern generation lies in two points; how to deal with a large number of faults, and what to do with faults that are hard to generate their test patterns. These problems can be resolved in a parallel-processing environment on a variable number of processors. Test-pattern generation is shown to be a good application of parallel processing techniques. The proposed method has been implemented on a multi-microcomputer system called LINKS-1 in order to estimate its performance. The results show that the proposed parallel processing method can get a high parallelism and achieve a high degree of acceleration of test-pattern generation.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Fast Test Pattern Generation Using a Multiprocessor System
T2 - IEICE TRANSACTIONS on transactions
SP - 441
EP - 447
AU - Hideo FUJIWARA
AU - Akira MOTOHARA
PY - 1988
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E71-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1988
AB - An approach for parallel processing of test-pattern generation for combinational circuits is described. In general, difficulty in test-pattern generation lies in two points; how to deal with a large number of faults, and what to do with faults that are hard to generate their test patterns. These problems can be resolved in a parallel-processing environment on a variable number of processors. Test-pattern generation is shown to be a good application of parallel processing techniques. The proposed method has been implemented on a multi-microcomputer system called LINKS-1 in order to estimate its performance. The results show that the proposed parallel processing method can get a high parallelism and achieve a high degree of acceleration of test-pattern generation.
ER -