Special Parallel Machine for LU Decomposition of a Large Scale Circuit Matrix and Its Performance

Nobuyuki TANAKA; Hideki ASAI

Special Parallel Machine for LU Decomposition of a Large Scale Circuit Matrix and Its Performance

Nobuyuki TANAKA, Hideki ASAI

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This paper describes the special purpose processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the LSI simulation. This processor is constructed by a division and several update clusters. Furthermore, each cluster has the plural processors and the special purpose circuits for label matching of the sparse matrix stored according to the packing scheme. After proposal of the architecture, we estimate the performance of SMASH for LU decomposition of the sparse matrix corresponding to a concrete circuit. As the result of that, we find that SMASH shows the high performance when it has the practical number of processor elements. Moreover, it is shown that the node tearing of the network is available for SMASH architecture.

Publication: IEICE TRANSACTIONS on transactions Vol.E72-E No.12 pp.1336-1343

Publication Date: 1989/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)

Category: VLSI Design Technology

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Nobuyuki TANAKA
Hideki ASAI

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Nobuyuki TANAKA, Hideki ASAI, "Special Parallel Machine for LU Decomposition of a Large Scale Circuit Matrix and Its Performance" in IEICE TRANSACTIONS on transactions, vol. E72-E, no. 12, pp. 1336-1343, December 1989, doi: .
Abstract: This paper describes the special purpose processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the LSI simulation. This processor is constructed by a division and several update clusters. Furthermore, each cluster has the plural processors and the special purpose circuits for label matching of the sparse matrix stored according to the packing scheme. After proposal of the architecture, we estimate the performance of SMASH for LU decomposition of the sparse matrix corresponding to a concrete circuit. As the result of that, we find that SMASH shows the high performance when it has the practical number of processor elements. Moreover, it is shown that the node tearing of the network is available for SMASH architecture.
URL: https://globals.ieice.org/en_transactions/transactions/10.1587/e72-e_12_1336/_p

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@ARTICLE{e72-e_12_1336,
author={Nobuyuki TANAKA, Hideki ASAI, },
journal={IEICE TRANSACTIONS on transactions},
title={Special Parallel Machine for LU Decomposition of a Large Scale Circuit Matrix and Its Performance},
year={1989},
volume={E72-E},
number={12},
pages={1336-1343},
abstract={This paper describes the special purpose processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the LSI simulation. This processor is constructed by a division and several update clusters. Furthermore, each cluster has the plural processors and the special purpose circuits for label matching of the sparse matrix stored according to the packing scheme. After proposal of the architecture, we estimate the performance of SMASH for LU decomposition of the sparse matrix corresponding to a concrete circuit. As the result of that, we find that SMASH shows the high performance when it has the practical number of processor elements. Moreover, it is shown that the node tearing of the network is available for SMASH architecture.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Special Parallel Machine for LU Decomposition of a Large Scale Circuit Matrix and Its Performance
T2 - IEICE TRANSACTIONS on transactions
SP - 1336
EP - 1343
AU - Nobuyuki TANAKA
AU - Hideki ASAI
PY - 1989
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E72-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1989
AB - This paper describes the special purpose processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the LSI simulation. This processor is constructed by a division and several update clusters. Furthermore, each cluster has the plural processors and the special purpose circuits for label matching of the sparse matrix stored according to the packing scheme. After proposal of the architecture, we estimate the performance of SMASH for LU decomposition of the sparse matrix corresponding to a concrete circuit. As the result of that, we find that SMASH shows the high performance when it has the practical number of processor elements. Moreover, it is shown that the node tearing of the network is available for SMASH architecture.
ER -