Large Scale Circuit Simulation System with Dedicated Parallel Processor SMASH

Nobuyuki TANAKA; Hideki ASAI

Large Scale Circuit Simulation System with Dedicated Parallel Processor SMASH

Nobuyuki TANAKA, Hideki ASAI

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This paper describes the circuit simulation system with dedicated parallel processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the circuit simulation. It shows the high performance when it has several decades of processor elements. First, we discuss the large scale circuit simulation system with SMASH and suggest the effcient interface of SMASH with the host computer with the consideration of circuit partitioning. This interface scheme uses the special structural memory unit constructed by 3 memory pages. By using this interface scheme, the host computer and SMASH can work independently. Furthemore, we estimate the performance of the simulation system. As the result of that, we show that the time required for the circuit simulation can be reduced to the evaluation time for element models. Moreover, it is shown that if the model evaluation is performed S times faster, the simulation speed also becomes S times faster by using SMASH and the interface scheme.

Publication: IEICE TRANSACTIONS on transactions Vol.E73-E No.12 pp.1957-1963

Publication Date: 1990/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems)

Category: Nonlinear Circuits and Simulation

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Nobuyuki TANAKA
Hideki ASAI

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Nobuyuki TANAKA, Hideki ASAI, "Large Scale Circuit Simulation System with Dedicated Parallel Processor SMASH" in IEICE TRANSACTIONS on transactions, vol. E73-E, no. 12, pp. 1957-1963, December 1990, doi: .
Abstract: This paper describes the circuit simulation system with dedicated parallel processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the circuit simulation. It shows the high performance when it has several decades of processor elements. First, we discuss the large scale circuit simulation system with SMASH and suggest the effcient interface of SMASH with the host computer with the consideration of circuit partitioning. This interface scheme uses the special structural memory unit constructed by 3 memory pages. By using this interface scheme, the host computer and SMASH can work independently. Furthemore, we estimate the performance of the simulation system. As the result of that, we show that the time required for the circuit simulation can be reduced to the evaluation time for element models. Moreover, it is shown that if the model evaluation is performed S times faster, the simulation speed also becomes S times faster by using SMASH and the interface scheme.
URL: https://globals.ieice.org/en_transactions/transactions/10.1587/e73-e_12_1957/_p

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@ARTICLE{e73-e_12_1957,
author={Nobuyuki TANAKA, Hideki ASAI, },
journal={IEICE TRANSACTIONS on transactions},
title={Large Scale Circuit Simulation System with Dedicated Parallel Processor SMASH},
year={1990},
volume={E73-E},
number={12},
pages={1957-1963},
abstract={This paper describes the circuit simulation system with dedicated parallel processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the circuit simulation. It shows the high performance when it has several decades of processor elements. First, we discuss the large scale circuit simulation system with SMASH and suggest the effcient interface of SMASH with the host computer with the consideration of circuit partitioning. This interface scheme uses the special structural memory unit constructed by 3 memory pages. By using this interface scheme, the host computer and SMASH can work independently. Furthemore, we estimate the performance of the simulation system. As the result of that, we show that the time required for the circuit simulation can be reduced to the evaluation time for element models. Moreover, it is shown that if the model evaluation is performed S times faster, the simulation speed also becomes S times faster by using SMASH and the interface scheme.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Large Scale Circuit Simulation System with Dedicated Parallel Processor SMASH
T2 - IEICE TRANSACTIONS on transactions
SP - 1957
EP - 1963
AU - Nobuyuki TANAKA
AU - Hideki ASAI
PY - 1990
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E73-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1990
AB - This paper describes the circuit simulation system with dedicated parallel processor SMASH. SMASH is the parallel machine with the specialized hardware for LU decomposition of a large scale sparse matrix required in the circuit simulation. It shows the high performance when it has several decades of processor elements. First, we discuss the large scale circuit simulation system with SMASH and suggest the effcient interface of SMASH with the host computer with the consideration of circuit partitioning. This interface scheme uses the special structural memory unit constructed by 3 memory pages. By using this interface scheme, the host computer and SMASH can work independently. Furthemore, we estimate the performance of the simulation system. As the result of that, we show that the time required for the circuit simulation can be reduced to the evaluation time for element models. Moreover, it is shown that if the model evaluation is performed S times faster, the simulation speed also becomes S times faster by using SMASH and the interface scheme.
ER -