A Routing Method for Macro Cell VLSI Layout

Takashi KAMBE; Tokihito OKADA; Shin-ichi FUJIWARA; Chiyoshi YOSHIOKA

A Routing Method for Macro Cell VLSI Layout

Takashi KAMBE, Tokihito OKADA, Shin-ichi FUJIWARA, Chiyoshi YOSHIOKA

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An automatic routing method for macro cell VLSI layout is described. This method is distinctive in that a new channel definition algorithm is employed to reduce routing detours and that a rectilinear channel spacer" is used to optimize the channel routing. This method is combined with a floorplanning program which optimizes design quality globally. Some experimental results are also shown to evaluate the performance of this method.

Publication: IEICE TRANSACTIONS on transactions Vol.E73-E No.12 pp.1979-1988

Publication Date: 1990/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems)

Category: VLSI Design

Authors

Takashi KAMBE
Tokihito OKADA
Shin-ichi FUJIWARA
Chiyoshi YOSHIOKA

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Takashi KAMBE, Tokihito OKADA, Shin-ichi FUJIWARA, Chiyoshi YOSHIOKA, "A Routing Method for Macro Cell VLSI Layout" in IEICE TRANSACTIONS on transactions, vol. E73-E, no. 12, pp. 1979-1988, December 1990, doi: .
Abstract: An automatic routing method for macro cell VLSI layout is described. This method is distinctive in that a new channel definition algorithm is employed to reduce routing detours and that a rectilinear channel spacer" is used to optimize the channel routing. This method is combined with a floorplanning program which optimizes design quality globally. Some experimental results are also shown to evaluate the performance of this method.
URL: https://globals.ieice.org/en_transactions/transactions/10.1587/e73-e_12_1979/_p

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@ARTICLE{e73-e_12_1979,
author={Takashi KAMBE, Tokihito OKADA, Shin-ichi FUJIWARA, Chiyoshi YOSHIOKA, },
journal={IEICE TRANSACTIONS on transactions},
title={A Routing Method for Macro Cell VLSI Layout},
year={1990},
volume={E73-E},
number={12},
pages={1979-1988},
abstract={An automatic routing method for macro cell VLSI layout is described. This method is distinctive in that a new channel definition algorithm is employed to reduce routing detours and that a rectilinear channel spacer" is used to optimize the channel routing. This method is combined with a floorplanning program which optimizes design quality globally. Some experimental results are also shown to evaluate the performance of this method.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Routing Method for Macro Cell VLSI Layout
T2 - IEICE TRANSACTIONS on transactions
SP - 1979
EP - 1988
AU - Takashi KAMBE
AU - Tokihito OKADA
AU - Shin-ichi FUJIWARA
AU - Chiyoshi YOSHIOKA
PY - 1990
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E73-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1990
AB - An automatic routing method for macro cell VLSI layout is described. This method is distinctive in that a new channel definition algorithm is employed to reduce routing detours and that a rectilinear channel spacer" is used to optimize the channel routing. This method is combined with a floorplanning program which optimizes design quality globally. Some experimental results are also shown to evaluate the performance of this method.
ER -