A multigate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) is a recently popular topic in the field of Si devices. In this study, self-aligned planar metal double-gate poly-Si TFTs consisting of an embedded bottom metal gate, a top metal gate fabricated by a self-alignment process, and a lateral poly-Si film with a grain size greater than 2 µm were fabricated on a glass substrate at 550. The nominal field-effect mobility of an n-channel TFT is 530 cm2/Vs, and its subthreshold slope is 140 mV/dec. The performance of the proposed TFTs is superior to that of top-gate TFTs fabricated using equivalent processes.

Enhancing the performance of low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) requires high-quality poly-Si films. One of the authors (A.H.) has already demonstrated a continuous-wave (CW) laser lateral crystallization (CLC) method to improve the crystalline quality of thin poly-Si films, using a diode-pumped solid-state CW laser. Another candidate method to increase the on-current and decrease the subthreshold swing (s.s.) is the use of a high-k gate stack. In this paper, we discuss the performance of top-gate CLC LT poly-Si TFTs with sputtering metal/hafnium oxide (HfO2) gate stacks on nonalkaline glass substrates. A mobility of 180 cm2/Vs is obtained for n-ch TFTs, which is considerably higher than those of previously reported n-ch LT poly-Si TFTs with high-k gate stacks; it is, however, lower than the one obtained with a plasma enhanced chemical vapor deposited SiO2 gate stack. For p-ch TFTs, a mobility of 92 cm2/Vs and an s.s. of 98 mV/dec were obtained. This s.s. value is smaller than the ones of the previously reported p-ch LT poly-Si TFTs with high-k gate stacks. The evaluation of a fabricated complementary metal-oxide-semiconductor inverter showed a switching threshold voltage of 0.8 V and a gain of 38 at an input voltage of 2.0 V; moreover, full swing inverter operation was successfully confirmed at the low input voltage of 1.0 V. This shows the feasibility of CLC LT poly-Si TFTs with a sputtered HfO2 gate dielectric on nonalkaline glass substrates.

Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below $550^{circ}$C, to realize high performance and low power dissipation system-on-glass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substrate and the TG was fabricated by a self-alignment process using the BG as a photomask. This structure is called embedded metal double-gate (E-MeDG) in this paper. The poly-Si channel with lateral large grains was fabricated using a continuous-wave laser lateral crystallization (CLC). The self-aligned 4T E-MeDG LT poly-Si TFT, with a gate length of 5,$mu $m and TG and BG SiO$_2$ thicknesses of 50 and 100,nm, respectively, exhibited a subthreshold swing of 120,mV/dec and a threshold voltage ($mathrm{V}_{mathrm{th}}$) of $-$0.5,V in the connecting DG mode; i.e. when TG is connected to BG. In the TG operation at various BG control voltage, a threshold voltage modulation factor $(gamma = Delta mathrm{V}_{mathrm{th}}/Delta mathrm{V}_{mathrm{BG}})$ of 0.47 at negative BG control voltage and 0.60 at positive BG control voltage are demonstrated, which values are nearly equal to theoretical prediction of 0.40 and 0.75. Trend of subthreshold swing (s.s.) of TG operation under different BG control voltage are also consistent with theoretical prediction. In addition to TG operation, successful BG operation under various TG control voltages was confirmed. Field-effect mobility derived from g$_{mathrm{m}}$ also varied depending on control gate voltage. The high controllability of device parameter of individual LT poly-Si TFTs is caused by excellent crystalline quality of CLC poly-Si film and will enable us to the fabrication of high-speed and low power-dissipation SoG.