This paper describes the delay time on bit lines due to coupling capacitance between adjacent bit lines in megabit SRAM's. The delay time on bit lines in several generations of megabit SRAM's is quantitatively analyzed using device and circuit simulations. It is shown that narrowing the bit-line swing from 200 mV to 30 mV for future 16-Mbit SRAM's will effectively reduce the difference in delay time from 1.0 ns to 0.3 ns, and that a two-block devided bit line will lower the difference in the delay-time ratio to 3% in case of 15-ns access time.

This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.