This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.

This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.

A new soft-error phenomenon in which the soft-error rate (SER) decreases as cycle time becomes shorter has been found in static RAM's (SRAM's) employing a high-resistive load memory cell. This inverted dependence is observed during the read cycle in the SRAM's involving the PMOS bit-line load. The SER at the cycle time of 100 ns is reduced by 1.5-orders of magnitude compared with that of conventional SRAM's. The convertional dependence of SER on cycle time has been explained with the time constant to charge up the "High" storage node potential through the high-resistive load. The mechanism of the inverted dependence becomes clear in consideration of the time constant of the potential drop of the "High" storage node. The analysis is applied to explain that three kinds of dependence of SER on cycle time, which are the conventional dependence, the inverted dependence, and no dependence, will be observed when the following cell parameters are changed. One is the threshold voltage of driver transistors in the cell, and the other is the impedance of the high-resistive load.

This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.

The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The Vt shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.

This letter describes the fan-out optimization method of the SRAM decoder having line capacitance that minimizes the total delay time. It is shown that the total delay time of the SRAM decoder optimized by this mothod is less than that of the equal fan-out condition.

This paper presents a pilot-aided channel estimation method which is particularly suitable for mobile WiMAX 802.16e Downlink Partial Usage of Subchannel mode. Based on this mode, several commonly used channel estimation methods are studied and the method of least squares line fitting is proposed. As data of users are distributed onto permuted clusters of subcarriers in the transmitted OFDMA symbol, the proposed channel estimation method utilizes these advantages to provide better performance than conventional approaches while offering remarkably low complexity in practical implementation. Simulation results with different ITU-channels for mobile environments show that depending on situations, enhancement of 5 dB or more in term of SNR can be achieved.

In this paper, an adaptive array antenna is implemented to enhance the performance of digital TV ISDB-T reception. Issues of realizing the proposed array antenna and its implementation by a joint hardware-software solution are also presented in this paper. Instead of using known reference signals, the proposed method utilizes the GI (Guard Interval) and a periodic property of OFDM signal as a constraint to realize MRC (Maximum Ratio Combining) and SMI (Sample Matrix Inversion) adaptive beam-forming algorithms. Experimental results show that the proposed system drastically improves the quality of reception. Moreover, the proposed system can achieve excellent performance under the conditions of strong interferences.