In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13 µm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.

We theoretically and experimentally demonstrate low loss branches in a Si photonic wire waveguide. Approximate calculation by the two-dimensional finite-difference time-domain (2-D FDTD) method and detailed design by the 3-D FDTD method indicate that low excess loss less than 0.2 dB is expected for a µm-size bend-waveguide-type branch at a wavelength of 1.55 µm. This branch is fabricated in a silicon-on-insulator substrate and the loss is evaluated to be 0.3 dB. This value is small enough to construct a very compact branching circuit.