Routing Methodology for Minimizing Crosstalk in SoC

Takashi YAMADA; Atsushi SAKAI; Yoshifumi MATSUSHITA; Hiroto YASUURA

Routing Methodology for Minimizing Crosstalk in SoC

Takashi YAMADA, Atsushi SAKAI, Yoshifumi MATSUSHITA, Hiroto YASUURA

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In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13 µm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.9 pp.2347-2356

Publication Date: 2003/09/01

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Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Takashi YAMADA, Atsushi SAKAI, Yoshifumi MATSUSHITA, Hiroto YASUURA, "Routing Methodology for Minimizing Crosstalk in SoC" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 9, pp. 2347-2356, September 2003, doi: .
Abstract: In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13 µm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/e86-a_9_2347/_p

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@ARTICLE{e86-a_9_2347,
author={Takashi YAMADA, Atsushi SAKAI, Yoshifumi MATSUSHITA, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Routing Methodology for Minimizing Crosstalk in SoC},
year={2003},
volume={E86-A},
number={9},
pages={2347-2356},
abstract={In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13 µm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Routing Methodology for Minimizing Crosstalk in SoC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2347
EP - 2356
AU - Takashi YAMADA
AU - Atsushi SAKAI
AU - Yoshifumi MATSUSHITA
AU - Hiroto YASUURA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2003
AB - In this paper, we propose new physical design techniques to reduce crosstalk noise and crosstalk-induced delay variations caused in a nanometer-scale system-on-a-chip (SoC). We have almost eliminated the coupling effect between signal wires by simply optimizing parameters for the automatic place and route methodology. Our approach consists of two techniques, (1) A 3-D optimization technique for tuning the routing grid configuration both in the horizontal and vertical directions. (2) A co-optimization technique for tuning the cell utilization ratio and the routing grid simultaneously. Experiments on the design of an image processing circuit fabricated in a 0.13 µm CMOS process with six layers of copper interconnect show that crosstalk noise is almost eliminated. From the results of a static timing analysis considering the worst-case crosstalk condition, the longest path delay is decreased by about 15% maximum if technique (1) is used, and by about 7% maximum if technique (2) is used. The 7-15% delay reduction has been achieved without process improvement, and this reduction corresponds to between 1/4 and 1/2 generation of process progress.
ER -