The Global Position System (GPS), which is well known as a global tool for positioning, is also the primary system for time transfer. GPS can deliver very precise time to every corner of the world. Usually, a GPS receiver indicates the precise time by means of the 1PPS (one pulse per second) signal. This paper studies the precise time transfer system structure of GPS receivers and then proposes an effective PPS signal generation method with predictive synchronous loop, combining phase error prediction and dynamic threshold adjustment. A GPS time transfer system is implemented and measured in detail to demonstrate the validity of the proposed algorithm. Assuming the receiver clock rate of 16.368MHz, the proposed method can achieve the accuracy of ±20ns in the scope 1δ which can meet the requirements of the vast majority of occasions. Through a long period of testing, we prove the feasibility of this algorithm experimentally.

Due to low signal-to-carrier ratio and high dynamic, the frequency deviation affects the bit synchronization in GNSS receiver. This paper proposes a balance differential coherent bit synchronization algorithm, which uses the differential coherent method to eliminate the influence of the frequency deviation. By enlarging the differential distance, the proposed algorithm achieves higher bit synchronization rates. Combining two complementary differential coherent parts, the proposed algorithm avoids the unbalance problem and the attenuation of accumulation. Furthermore, a general architecture is presented to reduce the system complexity. Experimental results show that the proposed algorithm improves the sensitivity of bit synchronization by 3∼7dB compared with the previous method.

With the decrease in transistor feature size, power consumption, especially leakage power, has become a most important design concern. Because of their superior electrical properties and design flexibility, fin-type field-effect transistors (FinFETs) seem to be the most promising option in low-power applications. In order to support the VLSI digital system design flow based on logic synthesis, this paper proposes a design method for low-power high-performance standard cells based on IG-mode FinFETs. Such a method is derived on the basis of appropriately and artfully designing and optimizing the stacked structures in each standard cell, and applying the mixed forward and reverse back-gate bias technique in a well-chosen manner. The proposed method is also applicable when the supply voltage reduces to 0.5V to further reduce the leakage power consumption. By applying this design method, optimized IG-mode FinFET standard cells are generated, and they form a low-power high-performance standard cell library. Simulation results of the library cells indicate that the performance of the standard cells designed with the proposed method can be maintained while reducing leakage consumption by a factor of 58.9 at most. The 16-bit ripple carry adder implemented with this library can acquire up to 17.5% leakage power reduction.

Forecasting commodity futures price is a challenging task. We present an algorithm to predict the trend of commodity futures price based on a type of structuring data and back propagation neural network. The random volatility of futures can be filtered out in the structuring data. Moreover, it is not restricted by the type of futures contract. Experiments show the algorithm can achieve 80% accuracy in predicting price trends.

Design of acoustic modem becomes increasingly important in underwater sensor networks' development. This paper presents the design of a reconfigurable acoustic modem, by defining modulation and demodulation as reconfigurable modules, the proposed modem changes its modulation scheme and data rate to provide reliable and energy efficient communication. The digital system, responsible for signal processing and control, is implemented on Xilinx Virtex5 FPGA. Hardware and software co-verification shows that the modem works correctly and can self-configure to BFSK and BPSK mode. Partial reconfiguration design method improves flexibility of algorithm design, and slice, LUT, register, DSP, RAMB are saved by 17%, 25%, 22%, 25%, 25% respectively.

The key factors in overcoming for weak global navigation satellite systems (GNSS) signal acquisition are sensitivity and dwell time. In the conventional MAX/TC criteria, a preset threshold value is used to determine whether the signal exists. Thus the threshold is calculated carefully to balance the sensitivity and the dwell time. Affected by various environment noise and interference, the acquisition circuit will enter verifying mode frequently to eliminate false alarms, which will extend the mean acquisition time (MAT). Based on the periodicity of spread spectrum code in GNSS, this paper presents an improved double-dwell scheme that uses no threshold in detecting weak GNSS signals. By adopting this method, the acquisition performance of weak signal is significantly improved. Theoretical analysis and numerical simulation are presented detailed. Compared with the conventional MAX/TC criteria, the proposed method achieves improved performance in terms of detection probability and false alarm rate. Furthermore, the MAT decreases 15s when C/N0 is above 20dB-Hz. This can enhance the receiver sensitivity and shorten the time to first fix (TTFF).

A novel application-dependent interconnect testing scheme of Xilinx Field Programmable Gate Arrays (FPGAs) based on line branches partitioning is presented. The targeted line branches of the interconnects in FPGAs' Application Configurations (ACs) are partitioned into multiple subsets, so that they can be tested with compatible Configurable Logic Blocks (CLBs) configurations in multiple Test Configurations (TCs). Experimental results show that for ISCAS89 and ITC99 benchmarks, this scheme can obtain a stuck-at fault coverage higher than 99% in less than 11 TCs.

The critical problem of the pseudo-noise (PN) code acquisition system is the contradiction between the acquisition performance and the calculation complexity. This paper presents a low cost correlator (LCC) structure that can search for two PN code phases in a single accumulation period by eliminating redundant computation. Compared with the part-parallel structure that is composed of two serial correlators (PARALLEL2), the proposed LCC structure has the same performance while saves about 22% chip area and 34% power consumption if uses the Carry-look-ahead (CLA) adder, 17% chip area and 25% power consumption if uses the Ripple-carry (RPL) adder.