A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 µm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4 the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.