An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors

Jim DUNNING; Gerald GARCIA; Jim LUNDBERG; Ed NUCKOLLS

An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors

Jim DUNNING, Gerald GARCIA, Jim LUNDBERG, Ed NUCKOLLS

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A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 µm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4 the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.660-670

Publication Date: 1995/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))

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Jim DUNNING
Gerald GARCIA
Jim LUNDBERG
Ed NUCKOLLS

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Jim DUNNING, Gerald GARCIA, Jim LUNDBERG, Ed NUCKOLLS, "An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 6, pp. 660-670, June 1995, doi: .
Abstract: A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 µm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4 the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_6_660/_p

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@ARTICLE{e78-c_6_660,
author={Jim DUNNING, Gerald GARCIA, Jim LUNDBERG, Ed NUCKOLLS, },
journal={IEICE TRANSACTIONS on Electronics},
title={An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors},
year={1995},
volume={E78-C},
number={6},
pages={660-670},
abstract={A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 µm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4 the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors
T2 - IEICE TRANSACTIONS on Electronics
SP - 660
EP - 670
AU - Jim DUNNING
AU - Gerald GARCIA
AU - Jim LUNDBERG
AU - Ed NUCKOLLS
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1995
AB - A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 µm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4 the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.
ER -