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Zunchao LI Ruizhi ZHANG Feng LIANG Zhiyong YANG
Halo doping profile is used in nanoscale surrounding-gate MOSFETs to suppress short channel effect and improve current driving capability. Analytical surface potential and threshold voltage models are derived based on the analytical solution of Poisson's equation for the fully depleted symmetric and asymmetric halo-doped MOSFETs. The validity of the analytical models is verified using 3D numerical simulation. The performance of the halo-doped MOSFETs are studied and compared with the uniformly doped surrounding-gate MOSFETs. It is shown that the halo-doped channel can suppress threshold voltage roll-off and drain-induced barrier lowering, and improve carrier transport efficiency. The asymmetric halo structure is better in suppressing hot carrier effect than the symmetric halo structure.
Feng LIANG ShaoChong LEI ZhiBiao SHAO
An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.
Linfeng LIANG Jun WANG Jian SONG
An improved spectrum sensing method based on PN autocorrelation (PNAC) for Digital Terrestrial Television Multimedia Broadcasting (DTMB) system is proposed in this paper. The low bound of miss-detection probability and the decision threshold for a given false alarm probability are studied. The performances of proposed method and existing methods are compared through computer simulations under both non-time dispersive channel and time dispersive channel. Simulation results show that the proposed method has better performance than the original PNAC-based method, and is more robust to both carrier frequency offset (CFO) and time dispersion of the channel than the existing method based on PN cross-correlation (PNCC).
Xianyu WANG Cong LI Heyi LI Rui ZHANG Zhifeng LIANG Hai WANG
Visual object tracking is always a challenging task in computer vision. During the tracking, the shape and appearance of the target may change greatly, and because of the lack of sufficient training samples, most of the online learning tracking algorithms will have performance bottlenecks. In this paper, an improved real-time algorithm based on deep learning features is proposed, which combines multi-feature fusion, multi-scale estimation, adaptive updating of target model and re-detection after target loss. The effectiveness and advantages of the proposed algorithm are proved by a large number of comparative experiments with other excellent algorithms on large benchmark datasets.
Zunchao LI Jinpeng XU Linlin LIU Feng LIANG Kuizhi MEI
The asymmetrical halo and dual-material gate structure is used in the surrounding-gate metal-oxide-semiconductor field effect transistor (MOSFET) to improve the performance. By treating the device as three surrounding-gate MOSFETs connected in series and maintaining current continuity, a comprehensive drain current model is developed for it. The model incorporates not only channel length modulation and impact ionization effects, but also the influence of doping concentration and vertical electric field distributions. It is concluded that the device exhibits increased current drivability and improved hot carrier reliability. The derived analytical model is verified with numerical simulation.
Yefei ZHANG Zunchao LI Chuang WANG Feng LIANG
In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si1-xGex virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si1-xGex virtual substrate. The model is found to tally well with the device simulator.
Chuang WANG Zunchao LI Cheng LUO Lijuan ZHAO Yefei ZHANG Feng LIANG
A novel auto-tuning digital DC--DC converter is presented. In order to reduce the recovery time and undershoot, the auto-tuning control combines LnL, conventional PID and a predictive PID with a configurable predictive coefficient. A switch module is used to select an algorithm from the three control algorithms, according to the difference between the error signal and the two initially predefined thresholds. The detection and control logic is designed for both window delay line ADC and $Sigma Delta$ DPWM to correct the delay deviation. When the output of the converter exceeds the quantization range, the digital output of ADC is set at 0 or 1, and the delay line stops working to reduce power consumption. Theoretical analysis and simulations in the CSMC CMOS 0.5,$mu$m process are carried out to verify the proposed DC--DC converter. It is found that the converter achieves a power efficiency of more than 90% at heavy load, and reduces the recovery time and undershoot.
Zhaoxi FANG Feng LIANG Shaozhong ZHANG Xiaolin ZHOU
Timing asynchronism strongly degrades the performance of analog network coded (ANC) bi-directional transmission. This letter investigates receiver design for asynchronous broadband bi-directional transmission over frequency selective fading channels. Based on time domain oversampling, we propose fractionally spaced frequency domain minimum mean square error (MMSE) equalizers for bi-directional ANC based on orthogonal frequency division multiplexing (OFDM) and cyclic prefixed single carrier (CP-SC) radio access. Simulation results show that the proposed fractionally spaced equalizer (FSE) can eliminate the negative effect of timing misalignment in bi-directional transmissions.
Fingerprints are useful for biometric purposes because of their well known properties of distinctiveness and persistence over time. However, owing to skin conditions or incorrect finger pressure, original fingerprint images always contain noise. Especially, some of them contain useless components, which are often mistaken for the terminations that are an essential minutia of a fingerprint. Mathematical Morphology (MM) is a powerful tool in image processing. In this paper, we propose a linear time algorithm to eliminate impulsive noise and useless components, which employs generalized and ordinary morphological operators based on Euclidean distance transform. There are two contributions. The first is the simple and efficient MM method to eliminate impulsive noise, which can be restricted to a minimum number of pixels. We know the performance of MM is heavily dependent on structuring elements (SEs), but finding an optimal SE is a difficult and nontrivial task. So the second contribution is providing an automatic approach without any experiential parameter for choosing appropriate SEs to eliminate useless components. We have developed a novel algorithm for the binarization of fingerprint images [1]. The information of distance transform values can be obtained directly from the binarization phase. The results show that using this method on fingerprint images with impulsive noise and useless components is faster than existing denoising methods and achieves better quality than earlier methods.
Shaochong LEI Feng LIANG Zeye LIU Xiaoying WANG Zhen WANG
To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design.