Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock trees before the fabrication and adjusts the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. Although post-silicon delay tuning improves the yield, it increases circuit area and power consumption since the PDEs are inserted. In this paper, a PDE structure is taken into consideration to reduce the circuit area and the power consumption. Moreover, a delay selection algorithm, and a clustering method, in which some PDEs are merged into a PDE and the PDE is inserted for multiple registers, are proposed to reduce the circuit area and the power consumption. In computational experiments, the proposed method reduced the circuit area and the power consumption in comparison with an existing method.

Due to the progress of the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay variations. To recover the timing violations, delay tuning methods insert programmable delay elements called PDEs into the clock tree before fabrication and tune their delays after fabrication. The yield improvement of existing methods is not enough. In this paper, a delay tuning method of PDEs with an ordered finite set of delays is proposed for the yield improvement. The proposed delay tuning method is based on the modified Bellman-Ford algorithm. Therefore, its optimality is guaranteed and its time complexity is polynomial. In the experiments under Monte-Carlo simulation, the yield of the proposed method is improved higher when the number of delays in each PDE is increased.

In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, circuit performance is expected to be improved compared to complete-synchronous framework, in which the clock is distributed periodically and simultaneously to each register. To improve the circuit performance more, logic synthesis for general-synchronous framework is required. In this paper, under the assumption that any clock schedule is realized by an ideal clock distribution circuit, when two or more cell libraries are available, a technology mapping method which assigns a cell to each gate in the given logic circuit by using integer linear programming is proposed. In experiments, we show the effectiveness of the proposed technology mapping method.