Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework

Junki KAWAGUCHI; Hayato MASHIKO; Yukihide KOHIRA

doi:10.1587/transfun.E99.A.1366

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework

Junki KAWAGUCHI, Hayato MASHIKO, Yukihide KOHIRA

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In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, circuit performance is expected to be improved compared to complete-synchronous framework, in which the clock is distributed periodically and simultaneously to each register. To improve the circuit performance more, logic synthesis for general-synchronous framework is required. In this paper, under the assumption that any clock schedule is realized by an ideal clock distribution circuit, when two or more cell libraries are available, a technology mapping method which assigns a cell to each gate in the given logic circuit by using integer linear programming is proposed. In experiments, we show the effectiveness of the proposed technology mapping method.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.7 pp.1366-1373

Publication Date: 2016/07/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E99.A.1366

Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)

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Authors

Junki KAWAGUCHI
  the University of Aizu
Hayato MASHIKO
  the University of Aizu
Yukihide KOHIRA
  the University of Aizu

Keyword

general-synchronous framework, technology mapping, integer linear programming

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Junki KAWAGUCHI, Hayato MASHIKO, Yukihide KOHIRA, "Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework" in IEICE TRANSACTIONS on Fundamentals, vol. E99-A, no. 7, pp. 1366-1373, July 2016, doi: 10.1587/transfun.E99.A.1366.
Abstract: In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, circuit performance is expected to be improved compared to complete-synchronous framework, in which the clock is distributed periodically and simultaneously to each register. To improve the circuit performance more, logic synthesis for general-synchronous framework is required. In this paper, under the assumption that any clock schedule is realized by an ideal clock distribution circuit, when two or more cell libraries are available, a technology mapping method which assigns a cell to each gate in the given logic circuit by using integer linear programming is proposed. In experiments, we show the effectiveness of the proposed technology mapping method.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.1366/_p

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@ARTICLE{e99-a_7_1366,
author={Junki KAWAGUCHI, Hayato MASHIKO, Yukihide KOHIRA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework},
year={2016},
volume={E99-A},
number={7},
pages={1366-1373},
abstract={In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, circuit performance is expected to be improved compared to complete-synchronous framework, in which the clock is distributed periodically and simultaneously to each register. To improve the circuit performance more, logic synthesis for general-synchronous framework is required. In this paper, under the assumption that any clock schedule is realized by an ideal clock distribution circuit, when two or more cell libraries are available, a technology mapping method which assigns a cell to each gate in the given logic circuit by using integer linear programming is proposed. In experiments, we show the effectiveness of the proposed technology mapping method.},
keywords={},
doi={10.1587/transfun.E99.A.1366},
ISSN={1745-1337},
month={July},}

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TY - JOUR
TI - Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1366
EP - 1373
AU - Junki KAWAGUCHI
AU - Hayato MASHIKO
AU - Yukihide KOHIRA
PY - 2016
DO - 10.1587/transfun.E99.A.1366
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2016
AB - In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, circuit performance is expected to be improved compared to complete-synchronous framework, in which the clock is distributed periodically and simultaneously to each register. To improve the circuit performance more, logic synthesis for general-synchronous framework is required. In this paper, under the assumption that any clock schedule is realized by an ideal clock distribution circuit, when two or more cell libraries are available, a technology mapping method which assigns a cell to each gate in the given logic circuit by using integer linear programming is proposed. In experiments, we show the effectiveness of the proposed technology mapping method.
ER -