This paper discusses branch metric computation in the main decoder placed in an SST (Scarce State Transition) Viterbi decoder. The basic assumptions that all the message sequences are equally likely and that the channel is memoryless do not hold for the main decoder in an SST Viterbi decoder, when an inverse encoder or a pseudo-inverse encoder is used as a pre-decoder. Therefore, in contrast to a conventional method, an MAP (Maximum A Posteriori probability) estimation method itself, which is the starting point of the maximum likelihood decoding, has been applied to branch metric computation. Then, it has been clarified that the conventional branch metric computed in a usual SST Viterbi decoder happens to be equal to the branch metric derived using the MAP estimation method only for systematic codes. For general non-systematic codes, in particular, it has been found that it is impossible to decompose a path metric into such branch metrics that follow the original code trellis structure, because the branch metric derived at time k is also dependent on future state transitions.

A random pulse stream (RPS) generator was developed for the noise immunity test of various digital system including communication system. By using this RPS generator along with the composite noise generator (CNG) developed formerly, the Middleton's "Class A" noise could be generated, and the total system (RPS+CNG) became more general noise simulator. In this paper, the configuration of CNG with newly developed RPS generator, and a typical example of Class A noise generated by this system are shown.

We have designed a superconductor-semiconductor hybrid analog-to-digital (A/D) converter and experimentally evaluated its performance at sampling frequencies up to 18.6 GHz. The A/D converter consists of a superconductor front-end circuit and a semiconductor back-end circuit. The front-end circuit includes a sigma-delta modulator and an interface circuit, which is for transmitting data signal to the semiconductor back-end circuit. The semiconductor back-end circuit performs decimation filtering. The design of the modulator was modified to reduce effects of integrator leak and thermal noise on signal-to-noise ratio (SNR). Using the improved modulator design, we achieved a bit-accuracy close to the ideal value. The hybrid architecture enabled us to reduce the integration scale of the front-end circuit to fewer than 500 junctions. This simplicity makes feasible a circuit based on a high TC superconductor as well as on a low TC superconductor. The experimental results show that the hybrid A/D converter operated perfectly and that SNR was 84.8 dB (bit accuracy~13.8 bit) at a band width of 9.1 MHz. This converter has the highest performance of all sigma-delta A/D converters.

We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-Tc single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating ramp-edge Josephson junctions with IcRn products above 1 mV at 40 K and small Ic spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the Jc spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200 GHz at 40 K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-Δ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100 GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50 GHz.

This paper reviews our progress on the high-Tc superconducting (HTS) sampler development, covering from the circuit design to the latest experimental data in the sinusoidal and pulse waveform measurements. A computer simulation has revealed that our sampler circuit with an improved design enables waveform measurement with the bandwidth over 100 GHz even with the thermal noise at around 40 K. Using the HTS sampler circuits fabricated employing an improved layout, we demonstrated waveform measurements for sinusoidal signals with frequencies of up to 50 GHz, the upper limit of the signal generator we used, both in the voltage-input-type system with a high-frequency input line and in the current-input-type one with a superconducting pickup coil. In the pulse measurement using an on-chip sampler, we succeeded in observing pico-second-order-wide single flux quantum (SFQ) current pulses, suggesting the potential bandwidth of our HTS sampler of more than 125 GHz.

We have developed a strato-mesospheric ozone monitoring system with a low noise SIS mixer, which receives 110.836 GHz millimeter-wave emission due to the rotational transition of ozone molecules (J=61,560,6). The system is completely standalone. We derived the altitude profile of ozone density between 25 km and 80 km from the observed spectrum. The receiver noise temperature was as low as 17 K (DSB), so that the altitude profile could be obtained every 3-10 minutes. The monitoring system can operate continuously over one year without any maintenance work, because it utilizes a 4 K closed cycle helium refrigerator and reliable Nb/AIOx/Nb SIS junctions. We used two acousto-optical spectrometers (AOSs) as real-time spectrometers because of their high resolution and simple construction. In an up-to-date system, one AOS would have a band-width of 65 MHz and the other, a band-width of 250 MHz with resolutions of 40 kHz and 250 kHz, respectively. A computer controls the entire system and is also used to analyze measured data. In this paper, we present the principles of system operation, the latest performance and the construction of the system, and some observed data.

We report the results of experiments on a Josephson RAM having an access time of 590 ps and a power dissipation of 19 mW. To design such high-speed memory, we developed new gates and circuits and used high-speed techniques. This paper details the design of the 4K bit Josephson RAM.

In this paper, we describe our SFQ circuit design and measurement carried out in SRL-ISTEC. We are studying an oversampling sigma-delta modulator and a counter-type decimation filter with multistage structure for developing AD converters for software-defined radio application. We are also developing a superconducting memory, whose peripheral circuits are constructed with SFQ circuits.

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic element based on the quantum flux parametron. AQFP circuits can operate with energy dissipation near the thermodynamic and quantum limits by maximizing the energy efficiency of adiabatic switching. We have established the design methodology for AQFP logic and developed various energy-efficient systems using AQFP logic, such as a low-power microprocessor, reversible computer, single-photon image sensor, and stochastic electronics. We have thus demonstrated the feasibility of the wide application of AQFP logic in future information and communications technology. In this paper, we present a tutorial review on AQFP logic to provide insights into AQFP circuit technology as an introduction to this research field. We describe the historical background, operating principle, design methodology, and recent progress of AQFP logic.

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.