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[Author] Masayuki KAWABATA(3hit)

1-3hit
  • HTS Sampler with Improved Circuit Design and Layout

    Michitaka MARUYAMA  Hironori WAKANA  Tsunehiro HATO  Hideo SUZUKI  Keiichi TANABE  Koichiro UEKUSA  Takeshi KONNO  Nobuya SATO  Masayuki KAWABATA  

     
    INVITED PAPER

      Vol:
    E90-C No:3
      Page(s):
    579-587

    This paper reviews our progress on the high-Tc superconducting (HTS) sampler development, covering from the circuit design to the latest experimental data in the sinusoidal and pulse waveform measurements. A computer simulation has revealed that our sampler circuit with an improved design enables waveform measurement with the bandwidth over 100 GHz even with the thermal noise at around 40 K. Using the HTS sampler circuits fabricated employing an improved layout, we demonstrated waveform measurements for sinusoidal signals with frequencies of up to 50 GHz, the upper limit of the signal generator we used, both in the voltage-input-type system with a high-frequency input line and in the current-input-type one with a superconducting pickup coil. In the pulse measurement using an on-chip sampler, we succeeded in observing pico-second-order-wide single flux quantum (SFQ) current pulses, suggesting the potential bandwidth of our HTS sampler of more than 125 GHz.

  • A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC

    Yasuhide KURAMOCHI  Masayuki KAWABATA  Kouichiro UEKUSA  Akira MATSUZAWA  

     
    PAPER-Electronic Circuits

      Vol:
    E93-C No:11
      Page(s):
    1630-1637

    We present self-calibration techniques for an interleaved SAR (Successive Approximation Register) ADC. The calibration technique is based on hardware corrections for linearity of single stage, gain error and mismatch errors of parallel ADCs. The 4-interleaved 11-bit ADC has been fabricated in a 0.18-µm CMOS process. Using the calibrations, measurement and calculation results show that the differences of ramp characteristic among the 4-interleaving ADC can be decresased to under 0.63 LSB.

  • A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS

    Yasuhide KURAMOCHI  Akira MATSUZAWA  Masayuki KAWABATA  

     
    PAPER

      Vol:
    E92-A No:2
      Page(s):
    360-366

    We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118 µW at 1.8 V power supply. Also, the active area of ADC core is realized to be 0.027 mm2. The calibration improves the SNDR by 13.4 dB and the SFDR by 21.0 dB. The measured SNDR and SFDR at 1 kHz input are 55.2 dB and 73.2 dB respectively.

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