A novel SC (Switched-Capacitor) offset- and gain-compensated sample/hold circuit is presented. It is implemented by a new topology which reduces the effects due to the imperfections of op-amp. Simulation results indicate that the circuit achieves high accuracy without requiring high-quality components.

We introduce a novel neural network called the T-Model and investigates the learning ability of the T-Model neural network. A learning algorithm based on the least mean square (LMS) algorithm is used to train the T-Model and produces a very good result for the T-Model network. We present simulation results on several practical problems to illustrate the efficiency of the learning techniques. As a result, the T-Model network learns successfully, but the Hopfield model fails to and the T-Model learns much more effectively and more quickly than a multi-layer network.

A new arithmetic multiple-valued algebra with functional completeness is introduced. The algebra is called Neuro-Algebra for it has very similar formula and architecture to neural networks. Two canonical forms of multiple-valued functions of this Neuro-Algebra are presented. Since the arithmetic operations of the Neuro-Aglebra are basically a weighted-sum and a piecewise linear operations, their implementations are very simple and straightforward. Furthermore, the multiple-valued networks based on the Neuro-Algebra can be trained by the traditional back-propagation learning algorithm directly.

Switched-capacitor frequency-to-voltage and voltage-to-frequency converters integrable onto a small chip area are developed. Their conversion sensitivity is insensitive to non-ideal circuit elements. Therefore, both the converters allow the accurate conversion over the wide dynamic range.

This paper introduces a switched-voltage delay cell with differential inputs. It can be used as a building block for a range of analogue functions such as voltage-to-frenquency converter, A/D converter, etc. Applications incorporating the delay cell are presented. The performances are verified by simulations on PSpice.

We introduce a novel neural network with a trigonometric interconnection called the T-Model neural network in this paper. A VLSI implementation of the T-Model neural network based on CMOS current-mode circuits is also presented. The circuit is completely compatible with standard VLSI technology. A set of neuron-type elements of CMOS current-mode circuits is described and a very large scale neural network is also synthesized. The feasibility and the operation principle of the synthesis of the T-Model neural network using CMOS current-mode circuits are demonstrated and confirmed by experimental results of fabricated CMOS VLSI neural chips.

A model for a large network with an unidirectional linear respone (ULR) is proposed in this letter. This deterministic system has powerful computing properties in very close correspondence with earlier stochastic model based on McCulloch-Pitts neurons and graded neuron model based on sigmoid input-output relation. The exclusive OR problems and other digital computation properties of the earlier models also are present in the ULR model. Furthermore, many analog and continuous signal processing can also be performed using the simple ULR neural network. Several examples of the ULR neural networks for analog and continuous signal processing are presented and show extemely promising results in terms of performance, density and potential for analog and continuous signal processing. An algorithm for the ULR neural network is also developed and used to train the ULR network for many digital and analog as well as continuous problems successfully.

A novel comparator-based switched-capacitor voltage-to-frequency converter is presented. By using the op-amp as the comparator, it can be operated over wide frequency range. Conversion sensitivity is also insensitive to capacitance ratio and parasitic capacitances between each node and ground.

The novel switched-capacitor frequency-to-voltage converter without employing active component is proposed. Therefore, it is free from non-ideal factors of active components, such as offset voltage or open loop gain of op-amps.

A novel buffer-based switched-capacitor (SC) integrator integrable by a method of reducing capacitance ratio is presented. By this method, high Q sc filter can be made by realizable capacitance ratio on CMOS process. The proposed integrator can also be operated over wide frequency range because it uses a unity gain buffer (UGB).

This paper extends an earlier study on the T-Model neural network to its collective computational properties. We present arguments that it is necessary to use the half-interconnected T-Model networks rather than the fully-interconnected Hopfield model networks. The T-Model has been generated in response to a number of observed weaknesses in the Hopfield model. This paper identities these problems and show how the T-Model overcomes them. The T-Model network is essentially a feedforward network which does not produce a local minimum for computations. A concept for understanding the dynamics of the T-Model neural circuit is presented and its performance is also compared with the Hopfield model. The T-Model neural circuit is implemented and tested with standard CMOS technology. Simulations and experiments show that the T-Model allows immense collective network computations and does not produce a local minimum. High densities comparable to that of the Hopfield model implementations have also been achieved.

An adaptive fuzzy network (AFN) is described that can be used to implement most of fuzzy logic functions. We introduce a learning algorithm largely borrowed from backpropagation algorithm and train the AFN system for several typical fuzzy problems. Simulations show that an adaptive fuzzy network can be implemented with the proposed network and algorithm, which would be impractical for a conventional fuzzy system.

In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.