A direct gradient descent learning algorithm of energy function in Hopfield neural networks is proposed. The gradient descent learning is not performed on usual error functions, but the Hopfield energy functions directly. We demonstrate the algorithm by testing it on an analog-to-digital conversion and an associative memory problems.

This paper describes an MOS charge-mode version of a T-Model neural-based PCM encoder. The neural-based PCM encoding networks are designed, simulated and implemented using MOS charge-mode circuits. Simulation results are given for both the T-Model and the Hopfield model CMOS charge-mode PCM encoders, and demonstrate the T-Model neural-based one performs the PCM encoding perfectly, while the Hopfield one fails to.

This paper presents an optimum design method of reliable networks. This paper, first, discusses several design methods for undirected graphs. It is shown that one new method of them gives graphs with the minimum diameter in a certain domain. In order to obtain optimum graph when the number of nodes and degree are given, this paper next discusses a method to obtain modified graphs with larger connectivity and also with the minimum diameter from known graphs which have diameter 1 over the minimum.

A novel buffer-based switched-capacitor (SC) integrator integrable by a method of reducing capacitance ratio is presented. By this method, high Q sc filter can be made by realizable capacitance ratio on CMOS process. The proposed integrator can also be operated over wide frequency range because it uses a unity gain buffer (UGB).

In this letter, we demonstrate an experimental CMOS neural circuit towards an understanding of how particular computations can be performed by a T-Model neural network. The architecture and a digital hardware implementation of the learning T-Model network are presented. Our experimental results show that the T-Model allows immense collective network computations and powerful learning.

This paper extends an earlier study on the T-Model neural network to its collective computational properties. We present arguments that it is necessary to use the half-interconnected T-Model networks rather than the fully-interconnected Hopfield model networks. The T-Model has been generated in response to a number of observed weaknesses in the Hopfield model. This paper identities these problems and show how the T-Model overcomes them. The T-Model network is essentially a feedforward network which does not produce a local minimum for computations. A concept for understanding the dynamics of the T-Model neural circuit is presented and its performance is also compared with the Hopfield model. The T-Model neural circuit is implemented and tested with standard CMOS technology. Simulations and experiments show that the T-Model allows immense collective network computations and does not produce a local minimum. High densities comparable to that of the Hopfield model implementations have also been achieved.

In this letter, a linear variable resistor circuit using an FG-MOSFET (floating-gate MOSFET) is proposed. This is based on Schlarmann's variable resistor and is very simple. The advantage of the proposed circuit is a wide-input range. The utility of the proposed circuit was confirmed by HSPICE simulation with 1.2 µm CMOS process parameters. The simulation results are reported in this letter.

An adaptive fuzzy network (AFN) is described that can be used to implement most of fuzzy logic functions. We introduce a learning algorithm largely borrowed from backpropagation algorithm and train the AFN system for several typical fuzzy problems. Simulations show that an adaptive fuzzy network can be implemented with the proposed network and algorithm, which would be impractical for a conventional fuzzy system.

In this letter, two kinds of MOS operational transconductance amplifiers (OTAs) based on combiners are presented. Each OTA has the following advantages; one of the proposed OTAs (OTA-1) can be operated at low supply voltage and the other OTA (OTA-2) has wide bandwidth. Through HSPICE simulations with a standard 0.35 µm CMOS device parameters, the operation under the supply voltage of 1.5 V for OTA-1 and the -3 dB bandwidth of several gigahertz for OTA-2 are confirmed.

In this paper, we present a new analog multiplier with wide input range which is achieved by utilizing the variable threshold voltage characteristics of FG-MOSFET's. The performance of the proposed multiplier is evaluated through HSPICE simulation with 2.0 µm CMOS process parameters. From HSPICE simulation, we can find that the proposed multiplier can be operated at the supply voltage of 3.0 V with 3.0 Vp-p input range. Namely, the input voltage range of the multiplier is equal to the supply voltage. The maximum power consumption of the multiplier is 8.8 mW. The THD is 1.36% under the condition that the amplitude of the input signal is 3.0 Vp-p and the frequency is 1 MHz. Under the same condition, the linearity error is less than 0.5%. The -3 dB bandwidth of the proposed multiplier is 23 MHz.

This paper describes a new model of multiple-valued immune network based on biological immune response network. The model of multiple-valued immune network is formulated based on the analogy with the interaction between B cells and T cells in immune system. The model has a property that resembles immune response quite well. The immunity of the network is simulated and makes several experimentally testable predictions. Simulation results are given to a letter recognition application of the network and compared with binary ones. The simulations show that, beside the advantages of less categories, improved memory pattern and good memory capacity, the multiple-valued immune network produces a stronger noise immunity than binary one.

In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.

In this letter, we propose high-speed binary to residue converters for moduli 2n, 2n 1 without using look-up table. For integration of residue arithmetic circuit using a signed-digit (SD) number representation with ordinary binary system, the proposed circuits carry out the efficient conversion. Using SD adders instead of ordinary adders that are used in conventional binary to residue converter, the high-speed conversion without the carry propagation can be achieved. Thus, the proposed converter is independent of the size of modulus and can speed up the binary to residue conversion. On the simulation, the conversion delay times are 1.78 ns for modulus 210-1 and 1.73 ns for modulus 210+1 under the condition of 0.6 µm CMOS technology, respectively. The active area of the proposed converter for moduli 210 1 is 335 µm325 µm.

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.

In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.

A calibrating analog-to digital (A/D) converter employing a T-Model neural network is described. The T-Model neural-based A/D converter architecure is presented with particular emphasis on the elimination of local minimum of the Hopfield neural network. Furthermore, a teacher forcing algorithm is presented and used to synthesize the A/D converter and correct errors of the converter due to offset and device mismatch. An experimental A/D converter using standard 5-µm CMOS discrete IC circuits demonstrates high-performance analog-to-digital conversion and calibrating.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.

A technique for pulse code modulation (PCM) encoding using a T-Model neural network is described. Performance evaluation on both the T-Model and the Hopfield model neural-based PCM encoders is carried out with PSpice simulations. The PSpice simulations also show that the T-Model neural-based PCM encoder computes to a global minimum much more effectively and more quickly than the Hopfield one.

We introduce a novel neural network called the T-Model and investigates the learning ability of the T-Model neural network. A learning algorithm based on the least mean square (LMS) algorithm is used to train the T-Model and produces a very good result for the T-Model network. We present simulation results on several practical problems to illustrate the efficiency of the learning techniques. As a result, the T-Model network learns successfully, but the Hopfield model fails to and the T-Model learns much more effectively and more quickly than a multi-layer network.