A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.

In this work, a gate-all-around (GAA) tunneling field-effect transistor (TFET) with InGaAs/Si heterojunction for high-performance and low-standby power operations is studied. Gallium (Ga) compositon ($x)$ in In$_{1-x}$Ga$_{x}$As source substantially affects the physical properties related with device performances including lattice constant, bandgap energy, effective tunneling mass, channel mobility, and others. Thus, it is worthy investigating the effect of Ga fraction on performances of the proposed heterojunction TFET. For this goal, the device design and its performance evaluation are carried out by technology computer-aided design (TCAD). Direct-current (DC) performances are investigated in terms of on-state current ($I_{ m{on}})$, off-state current ($I_{ m{off}})$, current ratio ($I_{ m{on}}$/$I_{ m{off}})$, and subthreshold swing ($S$). Furthermore, it is shown that the device with an n-type Si insertion layer between source and channel demonstrates the enhanced DC characteristics.