This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore, total memory requirements can be minimized.

Gradient-based methods for the computation of the velocity from image sequences assume that the velocity field varies smoothly over image. This creates difficulties at regions where the image intensity changes abruptly such as the occluding contours or region boundaries. In this letter, we propose a method to overcome these difficulties by incorporating the information of discontinuities in image intensity into a standard local optimization method. The presented method is applied to the synthetic and real images. The results show that the velocity field computed by the proposed method is less blurred at region boundaries than that of the standard method.

In formulating the motion constraint equation, we implicitly take it for granted that the spatial and temporal sampling intervals are very small. In real situations, since the intervals cannot be considered sufficiently small, an error will be introduced into the constraint equation and consequently the velocity estimate will be subject to an error due to inaccuracy of the constraint equation. We perform some experiments to analyze the effect of sampling interval on motion estimation. The understanding of experimental results will provide an insight into necessity and amount of image filtering prior to the application of motion estimation.

A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.